C8051F709-GQR Silicon Labs, C8051F709-GQR Datasheet - Page 273

• Manufacturer Part Number: C8051F709-GQR
• Description: 8-bit Microcontrollers - MCU 8kB 32B EEPROM Cap Sense
• Manufacturer: Silicon Labs

Specifications of C8051F709-GQR

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit

33.2.2. 8-bit Timers with Auto-Reload
When T2SPLIT is set, Timer 2 operates as two 8-bit timers (TMR2H and TMR2L). Both 8-bit timers oper-
ate in auto-reload mode as shown in Figure 33.5. TMR2RLL holds the reload value for TMR2L; TMR2RLH
holds the reload value for TMR2H. The TR2 bit in TMR2CN handles the run control for TMR2H. TMR2L is
always running when configured for 8-bit Mode.
Each 8-bit timer may be configured to use SYSCLK, SYSCLK divided by 12, or the external oscillator clock
source divided by 8. The Timer 2 Clock Select bits (T2MH and T2ML in CKCON) select either SYSCLK or
the clock defined by the Timer 2 External Clock Select bit (T2XCLK in TMR2CN), as follows:
The TF2H bit is set when TMR2H overflows from 0xFF to 0x00; the TF2L bit is set when TMR2L overflows
from 0xFF to 0x00. When Timer 2 interrupts are enabled (IE.5), an interrupt is generated each time
TMR2H overflows. If Timer 2 interrupts are enabled and TF2LEN (TMR2CN.5) is set, an interrupt is gener-
ated each time either TMR2L or TMR2H overflows. When TF2LEN is enabled, software must check the
TF2H and TF2L flags to determine the source of the Timer 2 interrupt. The TF2H and TF2L interrupt flags
are not cleared by hardware and must be manually cleared by software.
External Clock / 8
T2MH
SYSCLK / 12
0
0
1
T2XCLK
T2XCLK
0
1
X
0
1
TMR2H Clock Source
SYSCLK / 12
External Clock / 8
SYSCLK
SYSCLK
Figure 33.5. Timer 2 8-Bit Mode Block Diagram
0
1
1
0
T
M
H
3
M
T
3
L
CKCON
M
T
2
H
M
T
2
L
M
T
1
M
T
0
TR2
S
C
A
1
S
C
A
0
Rev. 1.0
TCLK
TCLK
TMR2RLH
TMR2RLL
TMR2H
TMR2L
T2ML
0
0
1
Reload
Reload
T2XCLK
C8051F70x/71x
1
X
0
To SMBus
To ADC,
TF2CEN
T2SPLIT
T2XCLK
SMBus
TF2LEN
TF2H
TF2L
TR2
External Clock / 8
SYSCLK
TMR2L Clock Source
SYSCLK / 12
Interrupt
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