FDPC8012S Fairchild Semiconductor, FDPC8012S Datasheet

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FDPC8012S

Manufacturer Part Number
FDPC8012S
Description
MOSFET 25V Asymmetric Dual N-Channel Pwr Trench
Manufacturer
Fairchild Semiconductor
Datasheet

Specifications of FDPC8012S

Rohs
yes
Transistor Polarity
N-Channel
Drain-source Breakdown Voltage
25 V
Gate-source Breakdown Voltage
12 V
Continuous Drain Current
88 A
Resistance Drain-source Rds (on)
7.5 Ohms
Configuration
Dual Asymmetric
Maximum Operating Temperature
+ 150 C
Mounting Style
SMD/SMT
Package / Case
PowerClip 33
Fall Time
3 ns
Forward Transconductance Gfs (max / Min)
200 S
Gate Charge Qg
25 nC
Minimum Operating Temperature
- 55 C
Power Dissipation
2 W
Rise Time
3 ns
Typical Turn-off Delay Time
34 ns

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
FDPC8012S
Manufacturer:
AVAGO
Quantity:
500
Part Number:
FDPC8012S
Manufacturer:
ON/安森美
Quantity:
20 000
FDPC8012S Rev.C
©2012 Fairchild Semiconductor Corporation
FDPC8012S
PowerTrench
25V Asymmetric Dual N-Channel MOSFET
Features
Q1: N-Channel
Q2: N-Channel
MOSFET Maximum Ratings
Thermal Characteristics
Package Marking and Ordering Information
V
V
I
E
P
T
R
R
R
D
J
DS
GS
AS
D
θJA
θJA
θJC
Max r
Max r
Low inductance packaging shortens rise/fall times, resulting in
lower switching losses
MOSFET integration enables optimum layout for lower circuit
inductance and reduced switch node ringing
RoHS Compliant
, T
Symbol
Device Marking
STG
01OD/03OD
Pin 1
DS(on)
DS(on)
Top
= 7.0 mΩ at V
= 2.2 mΩ at V
Drain to Source Voltage
Gate to Source Voltage
Drain Current
Single Pulse Avalanche Energy
Power Dissipation for Single Operation
Power Dissipation for Single Operation
Operating and Storage Junction Temperature Range
Thermal Resistance, Junction to Ambient
Thermal Resistance, Junction to Ambient
Thermal Resistance, Junction to Case
3.3 mm x 3.3 mm
®
Power Clip
GS
GS
GND
= 4.5 V, I
= 4.5 V, I
FDPC8012S
GND
-Pulsed
-Continuous
Device
-Continuous
LSG
D
D
V+
= 12 A
= 23 A
(LSS
GND
Bottom
T
A
= 25 °C unless otherwise noted
(HSD
V+
SW
Parameter
SW
Power Clip 33
SW
Package
HSG
Pin 1
HSG
SW
SW
SW
1
General Description
This device includes two specialized N-Channel MOSFETs in a
dual package. The switch node has been internally connected to
enable easy placement and routing of synchronous buck
converters. The control MOSFET (Q1) and synchronous
SyncFET
efficiency.
Applications
Computing
Communications
General Purpose Point of Load
PAD10
GND(LSS)
TM
PAD9
V+(HSD)
Reel Size
(Q2) have been designed to provide optimal power
13 ”
T
T
T
T
C
A
A
A
(Note 4)
(Note 3)
= 25 °C
= 25 °C
= 25 °C
= 25 °C
LSG
GND
GND
V+
Tape Width
HSG
SW
SW
SW
151
0.8
1.6
77
13
12 mm
Q1
5.0
25
12
35
40
50
1a
1a
1c
1a
1c
-55 to +150
SW
135
0.9
63
2.0
26
120
181
Q2
3.5
25
12
88
December 2012
1b
www.fairchildsemi.com
1b
1d
1d
1b
3000 units
Quantity
Units
°C/W
GND
LSG
GND
mJ
V+
°C
W
V
V
A

Related parts for FDPC8012S

FDPC8012S Summary of contents

Page 1

... Package Marking and Ordering Information Device Marking Device 01OD/03OD FDPC8012S ©2012 Fairchild Semiconductor Corporation FDPC8012S Rev.C General Description This device includes two specialized N-Channel MOSFETs in a dual package. The switch node has been internally connected enable easy placement and routing of synchronous buck converters ...

Page 2

... Turn-Off Delay Time d(off) t Fall Time f Q Total Gate Charge g Q Gate to Source Gate Charge gs Q Gate to Drain “Miller” Charge gd ©2012 Fairchild Semiconductor Corporation FDPC8012S Rev °C unless otherwise noted J Test Conditions = 250 μ mA 250 μ ...

Page 3

... Q2 181 mJ is based on starting Pulsed Id limited by junction temperature,td<=10uS. Please refer to SOA curve for more details. ©2012 Fairchild Semiconductor Corporation FDPC8012S Rev °C unless otherwise noted J Test Conditions ...

Page 4

... μ PULSE DURATION = 80 s DUTY CYCLE = 0.5% MAX 150 GATE TO SOURCE VOLTAGE (V) GS Figure 5. Transfer Characteristics ©2012 Fairchild Semiconductor Corporation FDPC8012S Rev 25°C unless otherwise noted 2 μ 0.6 0.8 1 ...

Page 5

... C/W θ JA DERIVED FROM TEST DATA A 0.01 0.01 0 DRAIN to SOURCE VOLTAGE (V) DS Figure 11. Forward Bias Safe Operating Area ©2012 Fairchild Semiconductor Corporation FDPC8012S Rev 25°C unless otherwise noted J 5000 = 10 V 1000 = 15 V 100 100 ...

Page 6

... Typical Characteristics (Q1 N-Channel) 2 DUTY CYCLE-DESCENDING ORDER 0.5 0.2 0.1 0.1 0.05 0.02 0.01 0.01 0.001 - Figure 13. ©2012 Fairchild Semiconductor Corporation FDPC8012S Rev 25°C unless otherwise noted J SINGLE PULSE 151 C/W θ JA (Note 1c RECTANGULAR PULSE DURATION (sec) Junction-to-Ambient Transient Thermal Response Curve ...

Page 7

... DUTY CYCLE = 0.5% MAX 100 125 1.0 1.5 2 GATE TO SOURCE VOLTAGE (V) GS Figure 18. Transfer Characteristics ©2012 Fairchild Semiconductor Corporation FDPC8012S Rev °C unless otherwise noted μ s 0.6 0.8 Figure 15. Normalized on-Resistance vs Drain 50 75 100 125 150 200 100 C o ...

Page 8

... 135 C/W θ JA DERIVED FROM o TEST DATA 0.01 0.01 0 DRAIN to SOURCE VOLTAGE (V) DS Figure 24. Forward Bias Safe Operating Area ©2012 Fairchild Semiconductor Corporation FDPC8012S Rev 25°C unless otherwise noted J 10000 100 ...

Page 9

... Typical Characteristics (Q2 N-Channel) 2 DUTY CYCLE-DESCENDING ORDER 1 0 0.5 0.2 0.1 0.05 0.01 0.02 0.01 1E-3 1E Figure 26. Junction-to-Ambient Transient Thermal Response Curve ©2012 Fairchild Semiconductor Corporation FDPC8012S Rev °C unless otherwise noted J SINGLE PULSE 135 C/W θ JA (Note 1d RECTANGULAR PULSE DURATION (sec) 9 ...

Page 10

... SyncFET Schottky body diode Characteristics TM Fairchild’s SyncFET process embeds a Schottky diode in parallel with PowerTrench MOSFET. This diode exhibits similar characteristics to a discrete external Schottky diode in parallel with a MOSFET. Figure 27 shows the reverse recovery characteristic of the FDPC8012S ...

Page 11

... LSG 8,PAD 9 V+, V+(HSD) PAD Table 1. Pin Information ©2012 Fairchild Semiconductor Corporation FDPC8012S Rev.C Description Gate signal input of Q1 Gate Switch or Phase node, Source of Q1 and Drain of Q2 Ground, Source of Q2 Gate signal input of Q2 Gate Input voltage of SR Buck converter, Drain www ...

Page 12

... FET packages. In most cases, board ground will be the most effective heat transfer path on the PCB. Use a large copper area between GND / GND(LSS)PAD pins and board ground. To ensure the best thermal and electrical connection to ground, we recommend using multiple vias to interconnect ground plane layers as shown in Figure 3. 1.Patent Pending ©2012 Fairchild Semiconductor Corporation FDPC8012S Rev.C 12 www.fairchildsemi.com ...

Page 13

... Vias should be relatively large, around 8 mils to 10 mils. "Avoid using narrow thermal relief traces on the V+ / V+(HSD) PAD and GND / GND(LSS)PAD pins. These will increase HF switch loop inductance. And these will increase ringing of the HF power loop and the SW node. ©2012 Fairchild Semiconductor Corporation FDPC8012S Rev.C 13 www.fairchildsemi.com ...

Page 14

... Dimensional Outline and Pad Layout ©2012 Fairchild Semiconductor Corporation FDPC8012S Rev.C 14 www.fairchildsemi.com ...

Page 15

... Datasheet Identification Product Status Advance Information Formative / In Design Preliminary First Production No Identification Needed Full Production Obsolete Not In Production ©2012 Fairchild Semiconductor Corporation FDPC8012S Rev.C ® PowerTrench PowerXS™ SM Programmable Active Droop™ ® QFET QS™ Quiet Series™ RapidConfigure™ ™ ...

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