TDGL007 Microchip Technology, TDGL007 Datasheet - Page 146

• Manufacturer Part Number: TDGL007
• Description: Development Boards & Kits - PIC / DSPIC DIGILENT CEREBOT MC7 MOTOR CONTROL BRD
• Manufacturer: Microchip Technology

Specifications of TDGL007

• Product: Development Boards
• Interface Type: CAN, I2C
• Operating Supply Voltage: 5 V

Oscillator
dsPIC33FJXXXMCX06A/X08A/X10A
9.1
There are seven system clock options provided by the
dsPIC33FJXXXMCX06A/X08A/X10A:
• FRC Oscillator
• FRC Oscillator with PLL
• Primary (XT, HS or EC) Oscillator
• Primary Oscillator with PLL
• Secondary (LP) Oscillator
• LPRC Oscillator
• FRC Oscillator with Postscaler
9.1.1
The FRC (Fast RC) internal oscillator runs at a nominal
frequency of 7.37 MHz. The user software can tune the
FRC frequency. User software can optionally specify a
factor (ranging from 1:2 to 1:256) by which the FRC
clock frequency is divided. This factor is selected using
the FRCDIV<2:0> bits (CLKDIV<10:8>).
The primary oscillator can use one of the following as
its clock source:
1.
2.
3.
The secondary (LP) oscillator is designed for low power
and uses a 32.768 kHz crystal or ceramic resonator.
The LP oscillator uses the SOSCI and SOSCO pins.
The LPRC (Low-Power RC) internal oscIllator runs at a
nominal frequency of 32.768 kHz. It is also used as a
reference clock by the Watchdog Timer (WDT) and
Fail-Safe Clock Monitor (FSCM).
The clock signals generated by the FRC and primary
oscillators can be optionally applied to an on-chip
Phase-Locked Loop (PLL) to provide a wide range of
output
configuration is described in
Configuration”.
The FRC frequency depends on the FRC accuracy
(see
Tuning register (see
9.1.2
The oscillator source that is used at a device Power-on
Reset event is selected using Configuration bit settings.
The oscillator Configuration bit settings are located in
the Configuration registers in the program memory.
(Refer to
details.) The Initial Oscillator Selection Configuration
bits, FNOSC<2:0> (FOSCSEL<2:0>), and the Primary
DS70594C-page 146
XT (Crystal): Crystals and ceramic resonators in
the range of 3 MHz to 10 MHz. The crystal is
connected to the OSC1 and OSC2 pins.
HS (High-Speed Crystal): Crystals in the range
of 10 MHz to 40 MHz. The crystal is connected
to the OSC1 and OSC2 pins.
EC (External Clock): External clock signal is
directly applied to the OSC1 pin.
Table
frequencies
CPU Clocking System
Section 23.1 “Configuration Bits”
26-19) and the value of the FRC Oscillator
SYSTEM CLOCK SOURCES
SYSTEM CLOCK SELECTION
Mode
Register
Select
for
device
9-4).
Configuration
Section 9.1.3 “PLL
operation.
for further
PLL
bits,
PLLDIV<8:0> bits (PLLFBD<8:0>), provides a factor, ‘M’,
frequency is in the range of 100 MHz to 200 MHz.
POSCMD<1:0> (FOSC<1:0>), select the oscillator
source that is used at a Power-on Reset. The FRC
primary oscillator is the default (unprogrammed)
selection.
The Configuration bits allow users to choose between
twelve different clock modes, shown in
The output of the oscillator (or the output of the PLL if a
PLL mode has been selected), F
generate the device instruction clock (F
peripheral clock time base (F
operating speed of the device and speeds up to 40 MHz
are supported by the dsPIC33FJXXXMCX06A/X08A/
X10A architecture.
Instruction execution speed or device operating
frequency, F
EQUATION 9-1:
9.1.3
The primary oscillator and internal FRC oscillator can
optionally use an on-chip PLL to obtain higher speeds
of operation. The PLL provides a significant amount of
flexibility in selecting the device operating speed. A
block diagram of the PLL is shown in
The output of the primary oscillator or FRC, denoted as
‘F
3, ... or 33 before being provided to the PLL’s Voltage
Controlled Oscillator (VCO). The input to the VCO must
be selected to be in the range of 0.8 MHz to 8 MHz.
Since the minimum prescale factor is 2, this implies that
F
16 MHz. The prescale factor, ‘N1’, is selected using the
PLLPRE<4:0> bits (CLKDIV<4:0>).
The
by which the input to the VCO is multiplied. This factor
must be selected such that the resulting VCO output
The VCO output is further divided by a postscale factor,
‘N2’. This factor is selected using the PLLPOST<1:0>
bits (CLKDIV<7:6>). ‘N2’ can be either 2, 4 or 8, and
must be selected such that the PLL output frequency
(F
generates device operating speeds of 6.25-40 MIPS.
For a primary oscillator or FRC oscillator output, ‘F
the PLL output, ‘F
equation:
EQUATION 9-2:
IN
IN
OSC
’, is divided down by a prescale factor (N1) of 2,
must be chosen to be in the range of 1.6 MHz to
) is in the range of 12.5 MHz to 80 MHz, which
PLL
PLL CONFIGURATION
CY
feedback
F
, is given by the following equation:
OSC
OSC
F
=
CY
DEVICE OPERATING
FREQUENCY
F
F
© 2011 Microchip Technology Inc.
divisor,
OSC
’, is given by the following
IN
=
⋅
F
-------------
CALCULATION
⎛
⎝
OSC
2
--------------------- -
N1
OSC
P
selected
M
⋅
). F
N2
, is divided by 2 to
Figure
CY
⎞
⎠
Table
CY
defines the
using
) and the
9-2.
9-1.
the
IN
’,