TDGL007 Microchip Technology, TDGL007 Datasheet - Page 257

• Manufacturer Part Number: TDGL007
• Description: Development Boards & Kits - PIC / DSPIC DIGILENT CEREBOT MC7 MOTOR CONTROL BRD
• Manufacturer: Microchip Technology

Specifications of TDGL007

• Product: Development Boards
• Interface Type: CAN, I2C
• Operating Supply Voltage: 5 V

23.0
dsPIC33FJXXXMCX06A/X08A/X10A devices include
several features intended to maximize application
flexibility and reliability, and minimize cost through
elimination of external components. These are:
• Flexible Configuration
• Watchdog Timer (WDT)
• Code Protection and CodeGuard™ Security
• JTAG Boundary Scan Interface
• In-Circuit Serial Programming™ (ICSP™)
• In-Circuit Emulation
TABLE 23-1:
© 2011 Microchip Technology Inc.
0xF80000 FBS
0xF80002 FSS
0xF80004 FGS
0xF80006 FOSCSEL
0xF80008 FOSC
0xF8000A FWDT
0xF8000C FPOR
0xF8000E FICD
0xF80010 FUID0
0xF80012 FUID1
0xF80014 FUID2
0xF80016 FUID3
Legend: — = unimplemented bit, reads as ‘0’.
Note 1:
Address
Note 1: This data sheet summarizes the features
2:
3:
2: Some registers and associated bits
SPECIAL FEATURES
These bits are reserved for use by development tools and must be programmed as ‘1’.
When read, this bit returns the current programmed value.
This bit is unimplemented on dsPIC33FJ64MCX06A/X08A/X10A and dsPIC33FJ128MCX06A/X08A/X10A
devices and reads as ‘0’.
of the dsPIC33FJXXXMCX06A/X08A/
X10A family of devices. However, it is
not intended to be a comprehensive ref-
erence source. To complement the infor-
mation in this data sheet, refer to Section
23.
(DS70199), Section 24. “Programming
and Diagnostics” (DS70207) and Sec-
tion
(DS70194) in the “dsPIC33F/PIC24H
Family Reference Manual”, which are
available from the Microchip web site
(www.microchip.com).
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization”
this data sheet for device-specific register
and bit information.
Name
DEVICE CONFIGURATION REGISTER MAP
25.
“CodeGuard™
dsPIC33FJXXXMCX06A/X08A/X10A
“Device
FWDTEN
PWMPIN
IESO
Bit 7
—
FCKSM<1:0>
Reserved
RBS<1:0>
RSS<1:0>
Configuration”
Reserved
WINDIS
HPOL
(1)
Bit 6
—
Security”
(2)
PLLKEN
in
JTAGEN
LPOL
Bit 5
—
—
—
—
—
(3)
User Unit ID Byte 0
User Unit ID Byte 1
User Unit ID Byte 2
User Unit ID Byte 3
23.1
dsPIC33FJXXXMCX06A/X08A/X10A devices provide
nonvolatile
configuration bits. Refer to Section 25. “Device Con-
figuration” (DS70194) of the “dsPIC33F/PIC24H
Family Reference Manual”, for more information on this
implementation.
The Configuration bits can be programmed (read as
‘0’), or left unprogrammed (read as ‘1’), to select
various device configurations. These bits are mapped
starting at program memory location 0xF80000.
The device Configuration register map is shown in
Table
The individual Configuration bit descriptions for the
Configuration registers are shown in
Note that address, 0xF80000, is beyond the user
program memory space. In fact, it belongs to the con-
figuration memory space (0x800000-0xFFFFFF) which
can only be accessed using table reads and table
writes.
WDTPRE
Bit 4
—
—
—
—
—
—
—
23-1.
Configuration Bits
memory
Bit 3
—
—
—
—
—
BSS<2:0>
SSS<2:0>
OSCIOFNC POSCMD<1:0>
WDTPOST<3:0>
implementation
GSS1
Bit 2
—
FNOSC<2:0>
FPWRT<2:0>
DS70594C-page 257
Table
GSS0
Bit 1
ICS<1:0>
for
23-2.
GWRP
BWRP
SWRP
Bit 0
device