AT45DB642D-TU Atmel, AT45DB642D-TU Datasheet

IC FLASH 64MBIT 66MHZ 28TSOP

AT45DB642D-TU

Manufacturer Part Number
AT45DB642D-TU
Description
IC FLASH 64MBIT 66MHZ 28TSOP
Manufacturer
Atmel
Datasheet

Specifications of AT45DB642D-TU

Format - Memory
FLASH
Memory Type
DataFLASH
Memory Size
64M (8192 pages x 1056 bytes)
Speed
66MHz
Interface
Parallel/Serial
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
28-TSOP
Density
64Mb
Access Time (max)
6ns
Interface Type
Parallel/Serial-SPI
Boot Type
Not Required
Address Bus
1/8Bit
Operating Supply Voltage (typ)
3.3V
Operating Temp Range
-40C to 85C
Package Type
TSOP-I
Program/erase Volt (typ)
2.7 to 3.6V
Sync/async
Synchronous
Operating Temperature Classification
Industrial
Operating Supply Voltage (min)
2.7V
Operating Supply Voltage (max)
3.6V
Word Size
8b
Number Of Words
8M
Supply Current
15mA
Mounting
Surface Mount
Pin Count
28
Data Bus Width
8 bit
Architecture
Sectored
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.7 V
Maximum Operating Current
15 mA
Mounting Style
SMD/SMT
Organization
256 KB x 32
Memory Configuration
8192 Pages X 1056 Bytes
Clock Frequency
66MHz
Supply Voltage Range
2.7V To 3.6V
Memory Case Style
TSOP
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Features
Single 2.7V - 3.6V Supply
Dual-interface Architecture
User Configurable Page Size
Page Program Operation
Flexible Erase Options
Two SRAM Data Buffers (1024/1056 Bytes)
Continuous Read Capability through Entire Array
Low-power Dissipation
Hardware and Software Data Protection Features
Permanent Sector Lockdown for Secure Code and Data Storage
Security: 128-byte Security Register
JEDEC Standard Manufacturer and Device ID Read
100,000 Program/Erase Cycles Per Page Minimum
Data Retention – 20 Years
Green (Pb/Halide-free/RoHS Compliant) Packaging Options
Temperature Range
– RapidS Serial Interface: 66 MHz Maximum Clock Frequency
– Rapid8 8-bit Interface: 50 MHz Maximum Clock Frequency
– 1024 Bytes per Page
– 1056 Bytes per Page
– Page Size Can Be Factory Pre-configured for 1024 Bytes
– Intelligent Programming Operation
– 8192 Pages (1024/1056 Bytes/Page) Main Memory
– Page Erase (1 Kbyte)
– Block Erase (8 Kbytes)
– Sector Erase (256 Kbytes)
– Chip Erase (64 Mbits)
– Allows Receiving of Data while Reprogramming the Flash Array
– Ideal for Code Shadowing Applications
– 10 mA Active Read Current Typical – Serial Interface
– 10 mA Active Read Current Typical – 8-bit Interface
– 25 µA Standby Current Typical
– 15 µA Deep Power Down Typical
– Individual Sector
– Individual Sector
– 64-byte User Programmable Space
– Unique 64-byte Device Identifier
– Industrial: -40°C to +85°C
SPI Compatible Modes 0 and 3
64-megabit
2.7-volt
Dual-interface
DataFlash
AT45DB642D
3542K–DFLASH–04/09
®

AT45DB642D-TU Summary of contents

Page 1

... JEDEC Standard Manufacturer and Device ID Read • 100,000 Program/Erase Cycles Per Page Minimum • Data Retention – 20 Years • Green (Pb/Halide-free/RoHS Compliant) Packaging Options • Temperature Range – Industrial: -40°C to +85°C 64-megabit 2.7-volt Dual-interface ® DataFlash AT45DB642D 3542K–DFLASH–04/09 ...

Page 2

... To allow for simple in-system reprogrammability, the AT45DB642D does not require high input voltages for programming. The device operates from a single power supply, 2.7V to 3.6V, for both the program and read operations. The AT45DB642D is enabled through the chip select pin (CS) and accessed via a three-wire interface consisting of the Serial Input (SI), Serial Output (SO), and the Serial Clock (SCK 8-bit interface consisting of the input/output pins (I/O7 - I/O0) and the clock pin (CLK) ...

Page 3

... RDY/BUSY and page-to-buffer transfers. The busy status indicates that the Flash memory array and one of the buffers cannot be accessed; read and write operations to the other buffer can still be performed. 3542K–DFLASH–04/09 ...

Page 4

... Figure 2-1. TSOP Top View: Type 1 RDY/BUSY 1 RESET VCC 6 GND SCK/CLK AT45DB642D 4 pin is used to supply the source voltage to the device. CC voltages may produce spurious results and should not be attempted I/O7 25 I/O6 24 I/O5 23 I/O4 22 VCCP 21 GNDP 20 I/O3 19 I/O2 18 I/O1 17 I/O0 16 ...

Page 5

... SER/BYTE 4. Memory Array To provide optimal flexibility, the memory array of the AT45DB642D is divided into three levels of granularity comprising of sectors, blocks, and pages. The “Memory Architecture Diagram” illus- trates the breakdown of each level and details the number of pages per sector and block. All program operations to the DataFlash occur on a page by page basis ...

Page 6

... The don’t care bytes that follow the address bytes are needed to initialize the read operation. Following the don’t care bytes, additional clock pulses on the SCK/CLK pin will result in data being output on either the SO (serial output) pin or the eight out- put pins (I/O7- I/O0). AT45DB642D 6 Table 15-1 on page 28 through Table 15-6 on 3542K– ...

Page 7

... The first 13 bits (PA12 - PA0) of the 24-bit address sequence specify which page of the main memory array to read, and the last 11 bits (BA10 - BA0) of the 24-bit address sequence specify the starting byte address within the page. To perform a contin- uous read with the page size set to 1024 bytes, the opcode, 03H, must be clocked into the device followed by three address bytes (A22 - A0) ...

Page 8

... BFA0). To perform a buffer read from the binary buffer (1024 bytes), the opcode must be clocked into the device followed by three address bytes comprised of 14 don’t care bits and 10 buffer address bits (BFA9 - BFA0). AT45DB642D 8 specification. The Main Memory Page Read bypasses SCK ...

Page 9

... DataFlash page size (1056 bytes), the opcode must be followed by three address bytes consist of 13 page address bits (PA12 - PA0) that specify the page in the main memory to be written and 11 don’t care bits. To perform a buffer to main memory page program with built-in erase for the ...

Page 10

... PA12/ PA11/ PA10/ PA9/ A22 A21 A20 A19 • • • • • • • • • • • • AT45DB642D 10 PA8/ PA7/ PA6/ PA5/ A18 A17 A16 A15 • • • • • • • • • • • • ...

Page 11

... The entire main memory can be erased at one time by using the Chip Erase command. To execute the Chip Erase command, a 4-byte command sequence C7H, 94H, 80H and 9AH must be clocked into the device. Since the entire memory array erased, no address bytes need to be clocked into the device, and any data clocked in after the opcode will be ignored ...

Page 12

... Sector Protection Register. The status of whether or not sector protection has been enabled or disabled by either the software or the hardware controlled methods can be deter- mined by checking the Status Register. AT45DB642D 12 Byte 1 Chip Erase ...

Page 13

Software Sector Protection 8.1.1 Enable Sector Protection Command Sectors specified for protection in the Sector Protection Register can be protected from program and erase operations by issuing the Enable Sector Protection command. To enable the sector protection using the ...

Page 14

... WP Pin and Protection Status Time Period WP Pin Enable Sector Protection Command 1 High 2 Low Command Issued During Period High AT45DB642D 14 time. When the WP pin is deasserted; however, the sector protection WPE 2 Command Not Issued Previously – Issue Command X – Issue Command time) as long as the Enable Sec- ...

Page 15

... Sector Protection Register and before 3542K–DFLASH–04/09 Sector Protection Register Sector 0 (0a, 0b) (Page 0-7) Bit 7, 6 (1) 1. The default value for bytes 0 through 31 when shipped from Atmel is 00H don’t care 0 (0a, 0b) See Table 9 ...

Page 16

... The Sector Protection Register can be reprogrammed while the sector protection enabled or dis- abled. Being able to reprogram the Sector Protection Register with the sector protection enabled allows the user to temporarily disable the sector protection to an individual sector rather than dis- abling sector protection completely. AT45DB642D 16 Byte 1 3DH ...

Page 17

The Program Sector Protection Register command utilizes the internal SRAM buffer for process- ing. Therefore, the contents of the buffer will be altered from its previous state when this command is issued. Command Program Sector Protection Register Figure 9-3. Program ...

Page 18

... Sector Lockdown com- mand if necessary. Command Sector Lockdown Figure 10-1. Sector Lockdown CS Opcode Byte Each transition represents 8 bits AT45DB642D 18 Byte 1 3DH Opcode Opcode Opcode Address Byte 2 Byte 3 Byte 4 Bytes , during which time the Status P ...

Page 19

... Reading the Sector Lockdown Register The Sector Lockdown Register can be read to determine which sectors in the memory array are permanently locked down. To read the Sector Lockdown Register, the CS pin must first be asserted. Once the CS pin has been asserted, an opcode of 35H and a series of dummy bytes (3 dummy bytes if using the serial interface or 7 dummy bytes if using the 8-bit interface) must be clocked into the device via the SI or I/O7-O0 pins ...

Page 20

... Therefore not possible to only program the first two bytes of the register and then pro- gram the remaining 62 bytes at a later time. The Program Security Register command utilizes the internal SRAM buffer for processing. Therefore, the contents of the buffer will be altered from its previous state when this command is issued. AT45DB642D 20 Security Register • • • 0 ...

Page 21

Figure 10-3. Program Security Register CS Opcode Byte 1 Each transition represents 8 bits 10.2.2 Reading the Security Register The Security Register can be read by first asserting the CS pin and then ...

Page 22

... The operation is internally self-timed and should take place in a maximum time of t and the RDY/BUSY pin will indicate that the part is busy. AT45DB642D 22 ), the status register can be read or the RDY/BUSY can be XFR ), the status register and the RDY/BUSY pin will indicate that the part is busy ...

Page 23

... The device density is indicated using bits and 2 of the status register. For the AT45DB642D, the four bits are 1111 The decimal value of these four binary bits does not equate to the device density; the four bits represent a combinational code relating to differing densities of DataFlash devices ...

Page 24

... Deep Power-down, the device will return to the normal standby mode. Command Resume from Deep Power-down Figure 12-2. Resume from Deep Power-Down AT45DB642D 24 time. Once the device has entered the Deep Power-down mode, all EDPD ...

Page 25

... Configuration Register is a user-programmable nonvolatile regis- ter that allows the page size of the main memory to be configured for binary page size (1024 bytes) or standard DataFlash page size (1056 bytes). The “power of 2” page size is a one-time programmable configuration register and once the device is configured for “ ...

Page 26

... Manufacturer ID codes that are two, three or even four bytes long with the first byte(s) in the sequence being 7FH. A system should detect code 7FH as a “Continuation Code” and continue to read Manufacturer ID bytes. The first non-7FH byte would signify the last byte of Manufacturer ID data. For Atmel (and some other manufacturers), the Manufacturer ID data is comprised of only one byte. AT45DB642D 26 Bit 3 ...

Page 27

... Chip Erase 5. Main Memory Page to Buffer 1 (or 2) Transfer 6. Main Memory Page to Buffer 1 (or 2) Compare 7. Buffer 1 ( Main Memory Page Program with Built-in Erase 8. Buffer 1 ( Main Memory Page Program without Built-in Erase 9. Main Memory Page Program through Buffer 1 (or 2) 10. Auto Page Rewrite Group C commands consist of: 1 ...

Page 28

... Buffer 1 to Main Memory Page Program without Built-in Erase Buffer 2 to Main Memory Page Program without Built-in Erase Page Erase Block Erase Sector Erase Chip Erase Main Memory Page Program Through Buffer 1 Main Memory Page Program Through Buffer 2 AT45DB642D 28 Serial/8-bit Opcode Both D2H Both E8H ...

Page 29

... Additional Commands Command Main Memory Page to Buffer 1 Transfer Main Memory Page to Buffer 2 Transfer Main Memory Page to Buffer 1 Compare Main Memory Page to Buffer 2 Compare Auto Page Rewrite through Buffer 1 Auto Page Rewrite through Buffer 2 Deep Power-down Resume from Deep Power-down Status Register Read Manufacturer and Device ID Read 3542K– ...

Page 30

... B9h ABh D1h D2h D3h D4h D6h D7h E8h Notes Don’t Care A = Address Bit *The number with (*) is for 8-bit interface. AT45DB642D 30 Address Byte Address Byte N/A N/A N/A N/A N/A N ...

Page 31

Table 15-6. Detailed Bit-level Addressing Sequence for Standard DataFlash Page Size (1056 Bytes) Page Size = 1056 bytes Opcode Opcode 03h 0Bh 0 1 ...

Page 32

... RDY/BUSY bit of the status register or the RDY/BUSY pin to determine whether the program or erase operation was completed. Fixed tim- ing is not recommended. AT45DB642D 32 . During power-up, the internal Power-on Reset circuitry keeps the device in VCSL ...

Page 33

... Voltage Extremes referenced in the "Absolute Maximum Ratings" are intended to accommo- + 0.6V CC date short duration undershoot/overshoot condi- tions and does not imply or guarantee functional device operation at these levels for any extended period of time Ind. AT45DB642D -40°C to 85°C 2.7V to 3.6V 33 ...

Page 34

... Output Low Voltage OL V Output High Voltage OH Notes and I during a buffer read maximum. CC1 CC2 2. All inputs (SI, SCK, CS#, WP#, and RESET#) are guaranteed by design to be 5-Volt tolerant. AT45DB642D 34 Condition Min CS, RESET all inputs at IH CMOS levels CS, RESET all inputs at IH CMOS levels MHz ...

Page 35

Table 18-4. AC Characteristics – RapidS/Serial Interface Symbol Parameter f SCK Frequency SCK f SCK Frequency for Continuous Array Read CAR1 SCK Frequency for Continuous Array Read f CAR2 (Low Frequency) t SCK High Time WH t SCK Low Time ...

Page 36

... Block Erase Time (8,192/8,448 bytes Sector Erase Time (262,144/270,336 bytes RESET Pulse Width RST t RESET Recovery Time REC Note: Values are based on device characterization, not 100% tested in production. 19. Input Test Waveforms and Measurement Levels < (10 AT45DB642D 36 Min 9 9 0 DRIVING 1.5V ...

Page 37

Output Test Load 21. AC Waveforms Six different timing waveforms are shown below. Waveform 1 shows the SCK/CLK signal being low when CS makes a high-to-low transition, and waveform 2 shows the SCK/CLK signal being high when CS makes ...

Page 38

... Waveform 4 – RapidS Mode SCK/CLK HIGH 21.5 Waveform 5 – Rapid8 Mode SCK/CLK HIGH IMPEDANCE I/O7 - I/O0 (OUTPUT) I/O7 - I/O0 (INPUT) 21.6 Waveform 6 – Rapid8 Mode SCK/CLK HIGH Z I/O7 - I/O0 (OUTPUT) I/O7 - I/O0 (INPUT) AT45DB642D MHz) MAX CSS VALID OUT VALID MHz) MAX t t ...

Page 39

Utilizing the RapidS To take advantage of the RapidS function's ability to operate at higher clock frequencies, a full clock cycle must be used to transmit data back and forth across the serial bus. The DataFlash is designed to ...

Page 40

... Slave clocks out BYTE a (first output byte). F. Master clocks in BYTE a. G. Master clocks in BYTE h (last output byte). 21.9 Reset Timing CS SCK/CLK RESET SO or I/O7 - I/O0 (OUTPUT I/O7 - I/O0 (INPUT) Note: The CS signal should be in the high state before the RESET signal is deasserted. AT45DB642D 40 Function ...

Page 41

... CMD 8 bits 8 bits Page Address (A22 - A10) CMD 8 bits 8 bits (PA12 - PA0) (BA10 - BA0/BFA10 - BFA0) FLASH MEMORY ARRAY WRITE I/O INTERFACE SI 8 bits Byte/Buffer Address (A9 - A0/BFA9 - BFA0) 8 bits Byte/Buffer Address BUFFER 2 TO MAIN MEMORY PAGE PROGRAM BUFFER 2 (1024/1056 BYTES) ...

Page 42

... Read Operations The following block diagram and waveforms illustrate the various read sequences available. PAGE (1024/1056 BYTES) MAIN MEMORY PAGE TO BUFFER 1 BUFFER 1 (1024/1056 BYTES) BUFFER 1 AT45DB642D 42 BINARY PAGE SIZE 14 DON'T CARE + BFA9-BFA0 CMD X BFA7-0 X···X, BFA10-8 Starts self-timed erase/program operation ...

Page 43

... Main Memory Page Read I/O7 - I/O0 (INPUT I/O7 - I/O0 (OUTPUT) 23.2 Main Memory Page to Buffer Transfer (Data from Flash Page Read into Buffer I/O7 - I/O0 (INPUT I/O7 - I/O0 (OUTPUT) 23.3 Buffer Read Each transition represents 8 bits 3542K–DFLASH–04/09 ADDRESS FOR BINARY PAGE SIZE ...

Page 44

... Continuous Array Read (Legacy Opcode E8H SCK OPCODE MSB HIGH-IMPEDANCE SO 24.2 Continuous Array Read (Opcode 0BH SCK OPCODE MSB HIGH-IMPEDANCE SO 24.3 Continuous Array Read (Low Frequency: Opcode 03H SCK MSB HIGH-IMPEDANCE SO AT45DB642D ADDRESS BITS 32 DON'T CARE BITS MSB MSB ADDRESS BITS A23 - MSB MSB ...

Page 45

... Main Memory Page Read (Opcode: D2H SCK OPCODE MSB HIGH-IMPEDANCE SO 24.5 Buffer Read (Opcode D4H or D6H SCK OPCODE MSB HIGH-IMPEDANCE SO 24.6 Buffer Read (Low Frequency: Opcode D1H or D3H SCK MSB HIGH-IMPEDANCE SO 3542K–DFLASH–04/ ADDRESS BITS 32 DON'T CARE BITS MSB ...

Page 46

... Read Sector Protection Register (Opcode 32H SCK MSB HIGH-IMPEDANCE SO 24.8 Read Sector Lockdown Register (Opcode 35H SCK MSB HIGH-IMPEDANCE SO 24.9 Read Security Register (Opcode 77H SCK MSB HIGH-IMPEDANCE SO AT45DB642D OPCODE DON'T CARE MSB OPCODE DON'T CARE MSB OPCODE DON'T CARE ...

Page 47

Status Register Read (Opcode D7H SCK SI 1 MSB HIGH-IMPEDANCE SO 24.11 Manufacturer and Device Read (Opcode 9FH) CS SCK SI HIGH-IMPEDANCE SO Note: Each transition 3542K–DFLASH–04/ ...

Page 48

... ADDR (INPUT) I/O7-I/O0 HIGH IMPEDANCE (OUTPUT) 25.2 Main Memory Page Read (Opcode: D2H) CS CLK t SU I/07-I/O0 (INPUT) I/07-I/O0 (OUTPUT) 25.3 Buffer Read (Opcode: 54H or 56H) CS CLK t SU I/O7-I/O0 (INPUT) I/O7-I/O0 (OUTPUT) AT45DB642D DUMMY BYTES ADDR DATA OUT DATA DATA BINARY & STANDARD ...

Page 49

... This type of algorithm is used for applications in which the entire array is programmed sequentially, filling the array page-by- page page can be written using either a Main Memory Page Program operation or a Buffer Write operation followed by a Buffer to Main Memory Page Program operation. 3. The algorithm above shows the programming of a single page. The algorithm will be repeated sequentially for each page within the entire array. 3542K– ...

Page 50

... Other algorithms can be used to rewrite portions of the Flash array. Low-power applications may choose to wait until 10,000 cumulative page erase and program operations have accumulated before rewriting all pages of the sector. See application note AN-4 (“Using Atmel’s Serial DataFlash”) for more details. AT45DB642D 50 START ...

Page 51

... Ordering Information 27.1 Ordering Code Detail Atmel Designator Product Family Device Density 64 = 64-megabit Interface 2 = Dual Device Revision 3542K–DFLASH–04/ – Device Grade U = Matte Sn lead finish, industrial temperature range (-40°C to +85°C) Package Option CN = 8-lead CASON T = 28-lead 13.4 mm TSOP Ball BGA ...

Page 52

... Package AT45DB642D-CNU (3) AT45DB642D-CNU-SL954 (4) AT45DB642D-CNU-SL955 AT45DB642D-TU AT45DB642D-CU Notes: 1. The shipping carrier option is not marked on the devices. 2. Standard parts are shipped with the page size set to 1056 bytes. The user is able to configure these parts to a 1024-byte page size if desired. 3. Parts ordered with suffix SL954 are shipped in bulk with the page size set to 1024 bytes. Parts will have a 954 or SL954 marked on them ...

Page 53

Packaging Information 28.1 28T – TSOP, Type 1 Pin 1 Identifier Area e E Notes: 1. This package conforms to JEDEC reference MO-183. 2. Dimensions D1 and E do not include mold protrusion. Allowable protrusion 0.15 ...

Page 54

... All dimensions and tolerance conform to ASME Y 14.5M, 1994. 2. The surface finish of the package shall be EDM Charmille #24-27. 3. Unless otherwise specified tolerance: Decimal ±0.05, Angular ±2 4. Metal Pad Dimensions. 2325 Orchard Parkway San Jose, CA 95131 R AT45DB642D 54 D Top View Side View Pin1 Pad Corner L1 ...

Page 55

Ball Grid Array Dimensions in Millimeters and (Inches). Controlling dimension: Millimeters. 1.00 (0.039) REF 1.00 (0.0394) BSC NON-ACCUMULATIVE 1.00 (0.0394) BSC NON-ACCUMULATIVE 2325 Orchard Parkway San Jose, CA 95131 R 3542K–DFLASH–04/09 6.10(0.240) 5.90(0.232 8.10(0.319) 7.90(0.311) ...

Page 56

... B – November 2005 C – March 2006 D – July 2006 E – August 2006 F – August 2006 G – August 2007 H – April 2008 I – February 2009 J – March 2009 K - April 2009 AT45DB642D 56 History Initial release Changed t from 30 µ µs min. VCSL Changed t from max. PUW Changed t from max ...

Page 57

... Use Block Erase (opcode 50H alternative. The Block Erase function is not affected by the Chip Erase issue. 30.1.3 Resolution The Chip Erase feature may be fixed with a new revision of the device. Please contact Atmel for the estimated availability of devices with the fix. 3542K–DFLASH–04/09 57 ...

Page 58

... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...

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