AT45DB642D-TU Atmel, AT45DB642D-TU Datasheet - Page 37

• Manufacturer Part Number: AT45DB642D-TU
• Description: IC FLASH 64MBIT 66MHZ 28TSOP
• Manufacturer: Atmel

Specifications of AT45DB642D-TU

• Format - Memory: FLASH
• Memory Type: DataFLASH
• Memory Size: 64M (8192 pages x 1056 bytes)
• Speed: 66MHz
• Interface: Parallel/Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-TSOP
• Density: 64Mb
• Access Time (max): 6ns
• Interface Type: Parallel/Serial-SPI
• Boot Type: Not Required
• Address Bus: 1/8Bit
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP-I
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Synchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 8M
• Supply Current: 15mA
• Mounting: Surface Mount
• Pin Count: 28
• Data Bus Width: 8 bit
• Architecture: Sectored
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Current: 15 mA
• Mounting Style: SMD/SMT
• Organization: 256 KB x 32
• Memory Configuration: 8192 Pages X 1056 Bytes
• Clock Frequency: 66MHz
• Supply Voltage Range: 2.7V To 3.6V
• Memory Case Style: TSOP
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

20. Output Test Load
21. AC Waveforms
21.1
21.2
Note:
3542K–DFLASH–04/09
Waveform 1 – SPI Mode 0 Compatible (for Frequencies up to 66 MHz)
Waveform 2 – SPI Mode 3 Compatible (for Frequencies up to 66 MHz)
To operate the device at 50 MHz in SPI mode, the combined CPU setup time and rise/fall time should be less than 2 ns.
SCK/CLK
SCK/CLK
Six different timing waveforms are shown below. Waveform 1 shows the SCK/CLK signal being
low when CS makes a high-to-low transition, and waveform 2 shows the SCK/CLK signal being
high when CS makes a high-to-low transition. In both cases, output SO becomes valid while the
SCK/CLK signal is still low (SCK/CLK low time is specified as t
conform to RapidS serial interface but for frequencies up to 66 MHz. Waveforms 1 and 2 are
compatible with SPI Mode 0 and SPI Mode 3, respectively.
Waveform 3 and waveform 4 illustrate general timing diagram for RapidS serial interface. These
are similar to waveform 1 and waveform 2, except that output SO is not restricted to become
valid during the t
imum frequency = 66 MHz) of the RapidS serial case. Waveform 5 and waveform 6 are for 8-bit
Rapid8 interface over the full frequency range of operation (maximum frequency = 50 MHz).
CS
SO
SO
CS
SI
SI
HIGH IMPEDANCE
HIGH Z
t
CSS
t
SU
t
t
V
CSS
t
SU
WL
period. These timing waveforms are valid over the full frequency range (max-
VALID IN
t
WL
VALID IN
VALID OUT
t
WH
DEVICE
UNDER
t
TEST
WH
t
V
t
HO
t
H
t
H
t
WL
VALID OUT
30 pF
t
HO
t
CSH
t
CSH
HIGH IMPEDANCE
t
t
t
HIGH IMPEDANCE
t
DIS
CS
DIS
CS
WL
). Timing waveforms 1 and 2
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