TLE6232GP Infineon Technologies, TLE6232GP Datasheet - Page 6
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TLE6232GP
Manufacturer Part Number
TLE6232GP
Description
IC SW SMART 6-CH LOWSIDE PDSO36
Manufacturer
Infineon Technologies
Type
Low Sider
Datasheet
1.TLE6232GP.pdf
(20 pages)
Specifications of TLE6232GP
Input Type
SPI
Number Of Outputs
6
On-state Resistance
250 mOhm, 450 mOhm
Current - Output / Channel
550mA, 1.1A
Current - Peak Output
2A, 4A
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 150°C
Mounting Type
Surface Mount
Package / Case
DSO-36
Packages
PG-DSO-36
Thermal Class
Heatslug down
Id Nom
4 x 1, 2 x 0.5 A
Pin Count
36.0 Pins
Channels
6.0
Comment
general purpose (e.g. 4x injectors, 2x relays)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
SP000012541
SP000308875
SP000691110
TLE6232GP
TLE6232GPNT
TLE6232GPT
TLE6232GPT
TLE6232GPTR
TLE6232GPXT
SP000308875
SP000691110
TLE6232GP
TLE6232GPNT
TLE6232GPT
TLE6232GPT
TLE6232GPTR
TLE6232GPXT
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
TLE6232GP
Manufacturer:
Infineon
Quantity:
2 913
Part Number:
TLE6232GP
Manufacturer:
INFINEON/英飞凌
Quantity:
20 000
Electrical Characteristics cont.
Parameter and Conditions
V
(unless otherwise specified)
5. Diagnostic Functions
Open Load Detection Voltage
Short to Ground Detection Voltage
Diagnostic Current (incl. Leakage)
Current Limitation; Overload Threshold Current
Over-temperature Shutdown Threshold
Hysteresis
Fault Delay Time
6. SPI-Timing
Serial Clock Frequency (@ C
Serial Clock Period (1/fclk)
Serial Clock High Time
Serial Clock Low Time
Enable Lead Time (falling edge of
CLK
Enable Lag Time (falling edge of CLK to rising edge of
Data Setup Time (required time SI to falling of CLK)
Data Hold Time (falling edge of CLK to SI)
Disable Time
Transfer Delay Time
(
Data Valid Time
3
4
V2.3
CS
This time is necessary between two write accesses. To get the correct diagnostic information, the transfer delay
This parameter will not be tested but specified by design
time has to be extended to the maximum fault delay time t
S
= 4.5 to 5.5 V ; T
)
high time between two accesses)
4
j
3
= - 40 °C to + 150 °C ; Reset = H
SO
50pF)
CS
to rising edge of
U
U
C
C
C
OUTi,j
OUTi,j
L
L
L
Page
= 50 pF
= 100 pF
= 150 pF
= 14V
= 0V
d(fault)max
CS
6
) t
Symbol
V
V
I
-I
I
I
T
T
t
f
t
t
t
t
t
t
t
t
t
OUTi,j
D(lim) 1-4
D(lim) 5,6
d(fault)
SCK
p(SCK)
SCKH
SCKL
lead
lag
SU
H
DIS
dt
valid
OUTi,j
th(sd)
hys
= 200µs.
DS(OL)
DS(SHG)
Data Sheet TLE 6232 GP
Values
0.52*
V
0.32
V
325
50
3
1.5
170
5
60
DC
200
50
100
100
150
20
20
--
150
--
--
--
s
min
s
*
--
--
--
--
--
---
--
--
--
--
--
--
--
0.6*
V
0.4
580
130
4
2
--
10
120
typ
s
V
s
*
0.68*
V
0.48
V
980
250
6
3
200
20
240
5
--
--
--
--
--
--
--
100
--
100
120
150
max
s
s
2009-11-18
*
Unit
V
V
µA
µA
A
A
°C
K
µs
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns