ADC1415S125/DB,598 NXP Semiconductors, ADC1415S125/DB,598 Datasheet - Page 17

• Manufacturer Part Number: ADC1415S125/DB,598
• Description: BOARD DEMO FOR ADC1415S125
• Manufacturer: NXP Semiconductors
• Type: A/Dr

Specifications of ADC1415S125/DB,598

• Number Of Adc's: 1
• Number Of Bits: 14
• Sampling Rate (per Second): 125M
• Data Interface: Serial, SPI™
• Inputs Per Adc: 1 Differential
• Input Range: 1 ~ 2 Vpp
• Power (typ) @ Conditions: 840mW @ 125Msps
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: ADC1415S125
• Product: Data Conversion Development Tools
• Conversion Rate: 125 MSPS
• Resolution: 14 bit
• Interface Type: SMA
• For Use With/related Products: ADC1415S125
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-5094

NXP Semiconductors
11. Application information
ADC1415S_SER
Product data sheet
Fig 11. Spurious-free dynamic range as a function of
SFDR
(dBc)
90
86
82
78
74
70
0
common-mode input voltage (V
11.1.1 SPI and Pin control modes
0.5
11.1 Device control
1.0
The ADC1415S can be controlled via the Serial Peripheral Interface (SPI control mode) or
directly via the I/O pins (Pin control mode).
The device enters Pin control mode at power-up, and remains in this mode as long as pin
CS is held HIGH. In Pin control mode, the SPI pins SDIO, CS and SCLK are used as
static control pins.
SPI control mode is enabled by forcing pin CS LOW. Once SPI control mode has been
enabled, the device remains in this mode. The transition from Pin control mode to SPI
control mode is illustrated in
When the device enters SPI control mode, the output data standard and data format are
determined by the level on pin SDIO as soon as a transition is triggered by a falling edge
on CS.
Fig 13. Control mode selection.
1.5
2.0
2.5
V
SCLK/DFS
SDIO/ODS
All information provided in this document is subject to legal disclaimers.
I(cm)
001aam659
3.0
i(cm)
Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs
(V)
CS
)
Rev. 4 — 17 December 2010
3.5
two's complement
Pin control mode
Data format
LVDS DDR
Figure
Fig 12. Signal-to-noise ratio as a function of
13.
(dBFS)
SNR
75
73
71
69
67
65
offset binary
Data format
0
common-mode input voltage (V
CMOS
0.5
ADC1415S series
1.0
R/W
SPI control mode
1.5
W1
2.0
W0
005aaa039
2.5
A12
© NXP B.V. 2010. All rights reserved.
V
I(cm)
001aam660
3.0
i(cm)
(V)
)
3.5
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