ADC1415S125/DB,598 NXP Semiconductors, ADC1415S125/DB,598 Datasheet - Page 18

• Manufacturer Part Number: ADC1415S125/DB,598
• Description: BOARD DEMO FOR ADC1415S125
• Manufacturer: NXP Semiconductors
• Type: A/Dr

Specifications of ADC1415S125/DB,598

• Number Of Adc's: 1
• Number Of Bits: 14
• Sampling Rate (per Second): 125M
• Data Interface: Serial, SPI™
• Inputs Per Adc: 1 Differential
• Input Range: 1 ~ 2 Vpp
• Power (typ) @ Conditions: 840mW @ 125Msps
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: ADC1415S125
• Product: Data Conversion Development Tools
• Conversion Rate: 125 MSPS
• Resolution: 14 bit
• Interface Type: SMA
• For Use With/related Products: ADC1415S125
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-5094

NXP Semiconductors
ADC1415S_SER
Product data sheet
11.1.2 Operating mode selection
11.1.3 Selecting the output data standard
11.1.4 Selecting the output data format
11.2.1 Input stage
11.2 Analog inputs
The active ADC1415S operating mode (Power-up, Power-down or Sleep) can be selected
via the SPI interface (see
described in
Table 10.
The output data standard (CMOS or LVDS DDR) can be selected via the SPI interface
(see
HIGH, otherwise CMOS is selected.
The output data format can be selected via the SPI interface (offset binary, two’s
complement or gray code; see
binary or two’s complement). Offset binary is selected when DFS is LOW. When DFS is
HIGH, two’s complement is selected.
The analog input of the ADC1415S supports a differential or a single-ended input drive.
Optimal performance is achieved using differential inputs. The ADC inputs are internally
biased and need to be decoupled.
The full-scale analog input voltage range is configurable between 1 V (p-p) and 2 V (p-p)
via a programmable internal reference (see
The equivalent circuit of the input buffer followed by the Sample and Hold (S/H) input
stage, including ElectroStatic Discharge (ESD) protection and circuit and package
parasitics, is shown in
Pin PWD
0
0
1
1
Table
Operating mode selection via pin PWD and OE
23) or using pin ODS in Pin control mode. LVDS DDR is selected when ODS is
Table
All information provided in this document is subject to legal disclaimers.
Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs
10.
Rev. 4 — 17 December 2010
Figure
Pin OE
0
1
0
1
Table
14.
Table
19) or using pins PWD and OE in Pin control mode, as
23) or using pin DFS in Pin control mode (offset
Operating mode
Power-up
Power-up
Sleep
Power-down
Section 11.3
ADC1415S series
and
Table
21).
Output high-Z
no
yes
yes
yes
© NXP B.V. 2010. All rights reserved.
18 of 42