ADC1415S125/DB,598 NXP Semiconductors, ADC1415S125/DB,598 Datasheet - Page 24

• Manufacturer Part Number: ADC1415S125/DB,598
• Description: BOARD DEMO FOR ADC1415S125
• Manufacturer: NXP Semiconductors
• Type: A/Dr

Specifications of ADC1415S125/DB,598

• Number Of Adc's: 1
• Number Of Bits: 14
• Sampling Rate (per Second): 125M
• Data Interface: Serial, SPI™
• Inputs Per Adc: 1 Differential
• Input Range: 1 ~ 2 Vpp
• Power (typ) @ Conditions: 840mW @ 125Msps
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: ADC1415S125
• Product: Data Conversion Development Tools
• Conversion Rate: 125 MSPS
• Resolution: 14 bit
• Interface Type: SMA
• For Use With/related Products: ADC1415S125
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-5094

NXP Semiconductors
ADC1415S_SER
Product data sheet
11.4.2 Equivalent input circuit
11.4.3 Duty cycle stabilizer
11.4.4 Clock input divider
The equivalent circuit of the input clock buffer is shown in
voltage of the differential input stage is set via internal 5 kΩ resistors.
Single-ended or differential clock inputs can be selected via the SPI interface
(see
control bit SE_SEL.
If single-ended is implemented without setting bit SE_SEL to the appropriate value, the
unused pin should be connected to ground via a capacitor.
The duty cycle stabilizer can improve the overall performance of the ADC by
compensating the duty cycle of the input clock signal. When the duty cycle stabilizer is
active (bit DCS_EN = logic 1; see
cycles of between 30 % and 70 % (typical). When the duty cycle stabilizer is disabled
(DCS_EN = logic 0), the input clock signal should have a duty cycle of between 45 % and
55 %.
The ADC1415S contains an input clock divider that divides the incoming clock by a factor
of 2 (when bit CLKDIV = logic 1; see
higher clock frequency with better jitter performance, leading to a better SNR result once
acquisition has been performed.
Fig 24. Equivalent input circuit
Table
V
CLKM
CLKP
cm(clk)
20). If single-ended is enabled, the input pin (CLKM or CLKP) is selected via
= common-mode voltage of the differential input stage.
All information provided in this document is subject to legal disclaimers.
Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs
Package
Rev. 4 — 17 December 2010
ESD
Table
Table
Parasitics
20), the circuit can handle signals with duty
20). This feature allows the user to deliver a
ADC1415S series
SE_SEL
Figure
5 kΩ
V
cm(clk)
24. The common-mode
SE_SEL
5 kΩ
© NXP B.V. 2010. All rights reserved.
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