ADC1415S125/DB,598 NXP Semiconductors, ADC1415S125/DB,598 Datasheet - Page 33

• Manufacturer Part Number: ADC1415S125/DB,598
• Description: BOARD DEMO FOR ADC1415S125
• Manufacturer: NXP Semiconductors
• Type: A/Dr

Specifications of ADC1415S125/DB,598

• Number Of Adc's: 1
• Number Of Bits: 14
• Sampling Rate (per Second): 125M
• Data Interface: Serial, SPI™
• Inputs Per Adc: 1 Differential
• Input Range: 1 ~ 2 Vpp
• Power (typ) @ Conditions: 840mW @ 125Msps
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: ADC1415S125
• Product: Data Conversion Development Tools
• Conversion Rate: 125 MSPS
• Resolution: 14 bit
• Interface Type: SMA
• For Use With/related Products: ADC1415S125
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-5094

NXP Semiconductors
Table 21.
Default values are highlighted.
Table 22.
Default values are highlighted.
Table 23.
Default values are highlighted.
ADC1415S_SER
Product data sheet
Bit
7 to 4
3
2 to 0
Bit
7 to 2
1 to 0
Bit
7 to 5
4
3
2
Symbol
-
INTREF_EN
INTREF[2:0]
Symbol
-
IB_IBIAS[1:0]
Symbol
-
LVDS_CMOS
OUTBUF
OUTBUS_SWAP
Internal reference control register (address 0008h) bit description
Input buffer control register (address 0010h) bit description
Output data standard control register (address 0011h) bit description
Access
R/W
R/W
Access
R/W
Access
R/W
R/W
R/W
All information provided in this document is subject to legal disclaimers.
Value
0000
0
1
000
001
010
011
100
101
110
111
Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs
Value
000000
00
01
10
11
Value
000
0
1
0
1
0
1
Rev. 4 — 17 December 2010
Description
not used
programmable internal reference enable
programmable internal reference
disable
active
0 dB (FS = 2 V)
−1 dB (FS = 1.78 V)
−2 dB (FS = 1.59 V)
−3 dB (FS = 1.42 V)
−4 dB (FS = 1.26 V)
−5 dB (FS = 1.12 V)
−6 dB (FS = 1 V)
reserved
Description
not used
input buffer bias current
Description
not used
output data standard: LVDS DDR or CMOS
output buffers enable
output bus swapping
not used
medium
low
high
CMOS
LVDS DDR
output enabled
output disabled (high Z)
no swapping
output bus is swapped (MSB becomes LSB and vice versa)
ADC1415S series
© NXP B.V. 2010. All rights reserved.
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