ADC1415S125/DB,598 NXP Semiconductors, ADC1415S125/DB,598 Datasheet - Page 34

• Manufacturer Part Number: ADC1415S125/DB,598
• Description: BOARD DEMO FOR ADC1415S125
• Manufacturer: NXP Semiconductors
• Type: A/Dr

Specifications of ADC1415S125/DB,598

• Number Of Adc's: 1
• Number Of Bits: 14
• Sampling Rate (per Second): 125M
• Data Interface: Serial, SPI™
• Inputs Per Adc: 1 Differential
• Input Range: 1 ~ 2 Vpp
• Power (typ) @ Conditions: 840mW @ 125Msps
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: ADC1415S125
• Product: Data Conversion Development Tools
• Conversion Rate: 125 MSPS
• Resolution: 14 bit
• Interface Type: SMA
• For Use With/related Products: ADC1415S125
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-5094

NXP Semiconductors
Table 23.
Default values are highlighted.
Table 24.
Default values are highlighted.
Table 25.
Default values are highlighted.
Table 26.
Default values are highlighted.
ADC1415S_SER
Product data sheet
Bit
1 to 0
Bit
7 to 4
3
2 to 0
Bit
7 to 6
5 to 0
Bit
7 to 3
Symbol
DATA_FORMAT[1:0]
Symbol
-
DAVINV
DAVPHASE[2:0]
Symbol
-
DIG_OFFSET[5:0]
Symbol
-
Output data standard control register (address 0011h) bit description
Output clock register (address 0012h) bit description
Offset register (address 0013h) bit description
Test pattern register 1 (address 0014h) bit description
Access
R/W
Access
R/W
R/W
Access
R/W
Access
All information provided in this document is subject to legal disclaimers.
Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs
Value
00
01
10
11
Value
0000
0
1
000
001
010
011
100
101
110
111
Value
00
011111
...
000000
...
100000
Rev. 4 — 17 December 2010
Value
00000
output clock data valid (DAV) polarity
Description
not used
DAV phase select
normal
inverted
output clock shifted (ahead) by 3 ns
output clock shifted (ahead) by 2.5 ns
output clock shifted (ahead) by 2 ns
output clock shifted (ahead) by 1.5 ns
output clock shifted (ahead) by 1 ns
output clock shifted (ahead) by 0.5 ns
default value as defined in timing section
output clock shifted (delayed) by 0.5 ns
Description
output data format
Description
not used
digital offset adjustment
Description
not used
offset binary
two’s complement
gray code
offset binary
+31 LSB
...
0
...
−32 LSB
ADC1415S series
…continued
© NXP B.V. 2010. All rights reserved.
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