ADC1415S125/DB,598 NXP Semiconductors, ADC1415S125/DB,598 Datasheet - Page 26

• Manufacturer Part Number: ADC1415S125/DB,598
• Description: BOARD DEMO FOR ADC1415S125
• Manufacturer: NXP Semiconductors
• Type: A/Dr

Specifications of ADC1415S125/DB,598

• Number Of Adc's: 1
• Number Of Bits: 14
• Sampling Rate (per Second): 125M
• Data Interface: Serial, SPI™
• Inputs Per Adc: 1 Differential
• Input Range: 1 ~ 2 Vpp
• Power (typ) @ Conditions: 840mW @ 125Msps
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: ADC1415S125
• Product: Data Conversion Development Tools
• Conversion Rate: 125 MSPS
• Resolution: 14 bit
• Interface Type: SMA
• For Use With/related Products: ADC1415S125
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-5094

NXP Semiconductors
ADC1415S_SER
Product data sheet
11.5.2 Digital output buffers: LVDS DDR mode
The digital output buffers can be configured as LVDS DDR by setting bit LVDS_CMOS to
logic_1 (see
Each output should be terminated externally with a 100 Ω resistor (typical) at the receiver
side
Table
The default LVDS DDR output buffer current is set to 3.5 mA. It can be programmed via
the SPI (bits DAVI[1:0] and DATAI[1:0]; see
voltage levels.
Table 13.
LVDS_INT_TER[2:0]
000
001
010
011
100
Fig 26. LVDS DDR digital output buffer - externally terminated
Fig 27. LVDS DDR digital output buffer - internally terminated
(Figure
32).
LVDS DDR output register 2
26) or internally via SPI control bits LVDS_INT_TER[2:0] (see
Table
All information provided in this document is subject to legal disclaimers.
Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs
−
+
−
+
23).
Rev. 4 — 17 December 2010
3.5 mA
typ
3.5 mA
typ
100 Ω
+
−
+
−
VCCO
D
D
OGND
VCCO
D
D
OGND
n
n
x
x
P/D
M/D
P/D
M/D
Table
x + 1
n + 1
n + 1
x + 1
Resistor value (Ω)
no internal termination
300
180
110
150
P
P
M
M
31) in order to adjust the output logic
ADC1415S series
100 Ω
RECEIVER
RECEIVER
005aaa058
005aaa059
© NXP B.V. 2010. All rights reserved.
Figure 27
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and