MC56F8037EVM Freescale Semiconductor, MC56F8037EVM Datasheet - Page 104
MC56F8037EVM
Manufacturer Part Number
MC56F8037EVM
Description
BOARD EVAL FOR MC56F8037
Manufacturer
Freescale Semiconductor
Type
MCUr
Datasheet
1.MC56F8037EVM.pdf
(180 pages)
Specifications of MC56F8037EVM
Contents
Board, Cables, CD, Debugger
Silicon Manufacturer
Freescale
Core Architecture
56800/E
Core Sub-architecture
56800/E
Silicon Core Number
MC56F
Silicon Family Name
MC56F80xx
Kit Contents
MC56F8037EVM, USB-JTAG Adapter, Cables, CD
Rohs Compliant
Yes
For Use With/related Products
MC56F8037
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC56F8037EVM
Manufacturer:
Freescale Semiconductor
Quantity:
135
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6.3.9.7
This bit field is reserved. Each bit must be set to 0.
6.3.9.8
6.3.9.9
6.3.9.10
6.3.9.11
6.3.9.12
6.3.9.13
This bit field is reserved. It must be set to 0.
6.3.9.14
6.3.10
See
104
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Section 6.3.9
Base + $D
RESET
Write
Read
0 = The clock is not provided to the I
1 = The clock is enabled to the I
0 = The clock is not provided to the QSCI1 module (the QSCI1 module is disabled)
1 = The clock is enabled to the QSCI1 module
0 = The clock is not provided to the QSCI0 module (the QSCI0 module is disabled)
1 = The clock is enabled to the QSCI0 module
0 = The clock is not provided to the QSPI1 module (the QSPI1 module is disabled)
1 = The clock is enabled to the QSPI1 module
0 = The clock is not provided to the QSPI0 module (the QSPI0 module is disabled)
1 = The clock is enabled to the QSPI0 module
0 = The clock is not provided to the PWM module (the PWM module is disabled)
1 = The clock is enabled to the PWM module
Peripheral Clock Enable Register 1 (SIM_PCE1)
Reserved—Bits 9–7
Inter-Integrated Circuit IPBus Clock Enable (I2C)—Bit 6
QSCI 1 Clock Enable (QSCI1)—Bit 5
QSCI 0 Clock Enable (QSCI0)—Bit 4
QSPI 1 Clock Enable (QSPI1)—Bit 3
QSPI 0 Clock Enable (QSPI0)—Bit 2
Reserved—Bit 1
PWM Clock Enable (PWM)—Bit 0
15
Figure 6-11 Peripheral Clock Enable Register 1 (SIM_PCE1)
0
0
for general information about Peripheral Clock Enable registers.
PIT2
14
0
PIT1
13
0
PIT0
12
0
56F8037/56F8027 Data Sheet, Rev. 7
2
C module
11
0
0
2
C module (the I
10
0
0
9
0
0
8
0
0
2
C module is disabled)
TB3
7
0
TB2
6
0
TB1
5
0
TB0
4
0
TA3
3
0
Freescale Semiconductor
TA2
2
0
TA1
1
0
TA0
0
0
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