MC56F8037EVM Freescale Semiconductor, MC56F8037EVM Datasheet - Page 125

• Manufacturer Part Number: MC56F8037EVM
• Description: BOARD EVAL FOR MC56F8037
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of MC56F8037EVM

• Contents: Board, Cables, CD, Debugger
• Silicon Manufacturer: Freescale
• Core Architecture: 56800/E
• Core Sub-architecture: 56800/E
• Silicon Core Number: MC56F
• Silicon Family Name: MC56F80xx
• Kit Contents: MC56F8037EVM, USB-JTAG Adapter, Cables, CD
• Rohs Compliant: Yes
• For Use With/related Products: MC56F8037
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The power-saving modes provide additional power management options by disabling the clock,
reconfiguring the voltage regulator clock generation to manage power utilization, as shown in
Run, Wait, and Stop modes provide methods of enabling/disabling the peripheral and/or core clocking as
a group. Stop disable controls for an individual peripheral are provided in the SDn registers to override the
default behavior of Stop mode. By asserting a peripheral’s Stop disable bit, the peripheral clock continues
to operate in Stop mode. This is useful to generate interrupts which will recover the device from Stop mode
to Run mode. Standby mode provides normal operation but at very low speed and power utilization. It is
Freescale Semiconductor
Run
Wait
Stop
Standby
Power-Down
Mode
Core and memory
clocks enabled
Core and memory
clocks disabled
Master clock generation in the OCCS
remains operational, but the SIM disables
the generation of system and peripheral
clocks.
The OCCS generates the master clock at a
reduced frequency (400kHz). The PLL is
disabled and the high-speed peripheral
option is not available. System and
peripheral clocks operate at 200kHz.
Master clock generation in the OCCS is
completely shut down. All system and
peripheral clocks are disabled.
Table 6-2 Clock Operation in Power-Saving Modes
Core Clocks
56F8037/56F8027 Data Sheet, Rev. 7
Peripheral clocks
enabled
Peripheral clocks
enabled
Peripheral Clocks
Device is fully functional
Core executes WAIT instruction to enter this
mode.
Typically used for power-conscious applications.
Possible recoveries from Wait mode to Run
mode are:
1. Any interrupt
2. Executing a Debug mode entry command
during the 56800E core JTAG interface
3. Any reset (POR, external, software, COP)
Core executes STOP instruction to enter this
mode.
Possible recoveries from Stop mode to Run
mode are:
1. Interrupt from any peripheral configured in the
CTRL register to operate in Stop mode (TA0-3,
QSCI0, PIT0-1, CAN, CMPA-B)
2. Low-voltage interrupt
3. Executing a Debug mode entry command
using the 56800E core JTAG interface
4. Any reset (POR, external, software, COP)
The user configures the OCCS and SIM to select
the relaxation oscillator clock source (PRECS),
shut down the PLL (PLLPD), put the relaxation
oscillator in Standby mode (ROSB), and put the
large regulator in Standby (LRSTDBY). The
device is fully operational, but operating at a
minimum frequency and power configuration.
Recovery requires reversing the sequence used
to enter this mode (allowing for PLL lock time).
The user configures the OCCS and SIM to enter
Standby mode as shown in the previous
description, followed by powering down the
oscillator (ROPD). The only possible recoveries
from this mode are:
1. External Reset
2. Power-On Reset
Description
Power-Saving Modes
Table
6-2.
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