MC56F8037EVM Freescale Semiconductor, MC56F8037EVM Datasheet - Page 129

BOARD EVAL FOR MC56F8037

MC56F8037EVM

Manufacturer Part Number
MC56F8037EVM
Description
BOARD EVAL FOR MC56F8037
Manufacturer
Freescale Semiconductor
Type
MCUr
Datasheet

Specifications of MC56F8037EVM

Contents
Board, Cables, CD, Debugger
Silicon Manufacturer
Freescale
Core Architecture
56800/E
Core Sub-architecture
56800/E
Silicon Core Number
MC56F
Silicon Family Name
MC56F80xx
Kit Contents
MC56F8037EVM, USB-JTAG Adapter, Cables, CD
Rohs Compliant
Yes
For Use With/related Products
MC56F8037
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
MC56F8037EVM
Manufacturer:
Freescale Semiconductor
Quantity:
135
6.8 Interrupts
The SIM generates no interrupts.
Part 7 Security Features
The 56F8037/56F8027 offers security features intended to prevent unauthorized users from reading the
contents of the flash memory (FM) array. The 56F8037/56F8027’s flash security consists of several
hardware interlocks that prevent unauthorized users from gaining access to the flash array.
After flash security is set, an authorized user is still able to access on-chip memory if a user-defined
software subroutine, which reads and transfers the contents of internal memory via serial communication
peripherals, is included in the application software.
7.1 Operation with Security Enabled
After the user has programmed flash with the application code, the 56F8037/56F8027 can be secured by
programming the security word $0002 into program memory location $00 7FF7. This non-volatile word
will keep the device secured through reset and through power-down of the device. Refer to the flash
memory chapter in the 56F802x and 56F803x Peripheral Reference Manual for the details. When flash
security mode is enabled, the 56F8037/56F8027 will disable the core EOnCE debug capabilities. Normal
Freescale Semiconductor
SYS_CLK_DIV2
CKGEN_RST
2X SYS_CLK
SYS_CLK_D
MSTR_OSC
PERIP_RST
CORE_RST
SYS_CLK
RST
Maximum Delay = 64 OSC_CLK cycles for POR reset extension and 32 OSC_CLK cycles
Figure 6-29 Timing Relationships of Reset Signal to Clocks
Switch on falling OSC_CLK
96 MSTR_OSC cycles
56F8037/56F8027 Data Sheet, Rev. 7
32 SYS_CLK cycles delay
for Combined reset extension
Switch on falling SYS_CLK
Switch on falling SYS_CLK
32 SYS_CLK cycles delay
Interrupts
129

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