MC56F8037EVM Freescale Semiconductor, MC56F8037EVM Datasheet - Page 149

• Manufacturer Part Number: MC56F8037EVM
• Description: BOARD EVAL FOR MC56F8037
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of MC56F8037EVM

• Contents: Board, Cables, CD, Debugger
• Silicon Manufacturer: Freescale
• Core Architecture: 56800/E
• Core Sub-architecture: 56800/E
• Silicon Core Number: MC56F
• Silicon Family Name: MC56F80xx
• Kit Contents: MC56F8037EVM, USB-JTAG Adapter, Cables, CD
• Rohs Compliant: Yes
• For Use With/related Products: MC56F8037
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale Semiconductor
10.6 Phase Locked Loop Timing
10.7 Relaxation Oscillator Timing
1. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work correctly. The PLL
2. The core system clock will operate at 1/6 of the PLL output frequency.
3. This is the time required after the PLL is enabled to ensure reliable operation.
4. This is measured on the CLKO signal (programmed as System clock) over 264 System clocks at 32MHz System clock frequency
1. Output frequency after factory trim.
2. This is the time required from Standby to Normal mode transition.
3. J
4. See
External reference crystal frequency for the PLL
Internal reference relaxation oscillator frequency for the PLL
PLL output frequency
PLL lock time
Accumulated jitter using an 8MHz external crystal as the PLL source
Cycle-to-cycle jitter
Relaxation Oscillator output frequency
Normal Mode
Standby Mode
Relaxation Oscillator stabilization time
Cycle-to-cycle jitter. This is measured on the CLKO
signal (programmed prescaler_clock) over 264 clocks
Minimum tuning step size
Maximum tuning step size
Variation over temperature -40C to 150ºC
Variation over temperature 0C to 105ºC
is optimized for 8MHz input.
and using an 8MHz oscillator frequency.
A
is required to meet QSCI requirements.
Figure 10-5
3
Characteristic
2
(24 x reference frequency)
Characteristic
Table 10-12 Relaxation Oscillator Timing
2
1
4
56F8037/56F8027 Data Sheet, Rev. 7
4
Table 10-11 PLL Timing
1
3
Symbol
t
jitterrosc
t
roscs
f
op
4
Minimum
Symbol
—
—
—
—
—
—
—
t
jitterpll
f
f
t
rosc
f
J
osc
plls
op
A
+1.0 to -1.5 +3.0 to -3.0
Typical
0 to +1
8.05
200
400
Min
.08
40
96
—
—
—
—
1
4
+2.0 to -2.0
Typ
Maximum
192
350
40
—
8
8
Phase Locked Loop Timing
—
—
—
—
3
Max
0.37
100
—
—
—
—
MHz
Unit
kHz
ms
ps
%
%
%
%
MHz
MHz
MHz
Unit
µs
ps
%
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