MC56F8037EVM Freescale Semiconductor, MC56F8037EVM Datasheet - Page 107

• Manufacturer Part Number: MC56F8037EVM
• Description: BOARD EVAL FOR MC56F8037
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of MC56F8037EVM

• Contents: Board, Cables, CD, Debugger
• Silicon Manufacturer: Freescale
• Core Architecture: 56800/E
• Core Sub-architecture: 56800/E
• Silicon Core Number: MC56F
• Silicon Family Name: MC56F80xx
• Kit Contents: MC56F8037EVM, USB-JTAG Adapter, Cables, CD
• Rohs Compliant: Yes
• For Use With/related Products: MC56F8037
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.3.11.3
6.3.11.4
6.3.11.5
This bit field is reserved. It must be set to 0.
6.3.11.6
6.3.11.7
This bit field is reserved. Each bit must be set to 0.
6.3.11.8
6.3.11.9
6.3.11.10 QSCI0 Clock Stop Disable (QSCI0_SD)—Bit 4
6.3.11.11 QSPI1 Clock Stop Disable (QSPI1_SD)—Bit 3
6.3.11.12 QSPI0 Clock Stop Disable (QSPI0_SD)—Bit 2
Each bit controls clocks to the indicated peripheral.
Freescale Semiconductor
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0 = The clock is disabled during Stop mode
1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0
register
0 = The clock is disabled during Stop mode
1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0
register
0 = The clock is disabled during Stop mode
1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0
register
0 = The clock is disabled during Stop mode
1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0
register
0 = The clock is disabled during Stop mode
1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0
register
0 = The clock is disabled during Stop mode
1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0
register
0 = The clock is disabled during Stop mode
1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0
register
Digital-to-Analog Converter 1 Clock Stop Disable (DAC1_SD)—Bit 13
Digital-to-Analog Converter 0 Clock Stop Disable (DAC0_SD)—Bit 12
Reserved—Bit 11
Analog-to-Digital Converter Clock Stop Disable (ADC_SD)—Bit 10
Reserved—Bits 9–7
Inter-Integrated Circuit Clock Stop Disable (I2C_SD)—Bit 6
QSCI1 Clock Stop Disable (QSCI1_SD)—Bit 5
56F8037/56F8027 Data Sheet, Rev. 7
Register Descriptions
107