MC56F8037EVM Freescale Semiconductor, MC56F8037EVM Datasheet - Page 24

• Manufacturer Part Number: MC56F8037EVM
• Description: BOARD EVAL FOR MC56F8037
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of MC56F8037EVM

• Contents: Board, Cables, CD, Debugger
• Silicon Manufacturer: Freescale
• Core Architecture: 56800/E
• Core Sub-architecture: 56800/E
• Silicon Core Number: MC56F
• Silicon Family Name: MC56F80xx
• Kit Contents: MC56F8037EVM, USB-JTAG Adapter, Cables, CD
• Rohs Compliant: Yes
• For Use With/related Products: MC56F8037
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2.2 56F8037/56F8027 Signal Pins
After reset, each pin is configured for its primary function (listed first). Any alternate functionality must
be programmed.
24
Return to
(GPIOA7)
RESET
Signal
Name
V
V
V
V
V
V
V
V
V
V
V
DDA
SSA
CAP
CAP
DD
DD
DD
SS
SS
SS
SS
Table 2-3 56F8037/56F8027 Signal and Package Information for the 64-Pin LQFP
Table 2-2
Pin No.
LQFP
41
50
27
40
51
16
17
28
49
31
7
8
Input/Open
Supply
Supply
Supply
Supply
Supply
Output
Type
Drain
Input
State During
enabled
internal
Supply
Supply
Supply
Supply
Supply
pull-up
Reset
Input,
56F8037/56F8027 Data Sheet, Rev. 7
I/O Power — This pin supplies 3.3V power to the chip I/O interface.
V
ADC Power — This pin supplies 3.3V power to the ADC modules. It
must be connected to a clean analog power supply.
ADC Analog Ground — This pin supplies an analog ground to the
ADC modules.
V
order to bypass the core voltage regulator, required for proper chip
operation. See
Reset — This input is a direct hardware reset on the processor.
When RESET is asserted low, the chip is initialized and placed in the
reset state. A Schmitt trigger input is used for noise immunity. The
internal reset signal will be deasserted synchronous with the internal
clocks after a fixed number of internal clocks.
Port A GPIO — This GPIO pin can be individually programmed as
an input or open drain output pin. Note that RESET functionality is
disabled in this mode and the chip can only be reset via POR, COP
reset, or software reset.
After reset, the default state is RESET.
SS
CAP
— These pins provide ground for chip logic and I/O drivers.
— Connect this pin to a 2.2F or greater bypass capacitor in
Section
10.2.1.
Signal Description
Freescale Semiconductor