MPC8360E-RDK Freescale Semiconductor, MPC8360E-RDK Datasheet - Page 30

• Manufacturer Part Number: MPC8360E-RDK
• Description: BOARD REFERENCE DESIGN FOR MPC
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC II™ PROr
• Type: MPUr

Specifications of MPC8360E-RDK

• Contents: Board, Cables, CD, Power Supply
• Processor To Be Evaluated: MPC8360E
• Data Bus Width: 32 bit
• Interface Type: RS-232, Ethernet, USB
• Operating Supply Voltage: 1.3 V
• For Use With/related Products: MPC8360E
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

UCC Ethernet Controller: Three-Speed Ethernet, MII Management
Figure 10
8.2.1.2
Table 28
30
At recommended operating conditions with LV
At recommended operating conditions with LV
GTX_CLK clock fall time, (80% to 20%)
GTX_CLK125 clock period
GTX_CLK125 reference clock duty cycle measured at
LV
Notes:
1. The symbols used for timing specifications follow the pattern t
2. This symbol is used to represent the external GTX_CLK125 signal and does not follow the original symbol naming
3. In rev. 2.0 silicon, due to errata, t
RX_CLK clock period
RX_CLK duty cycle
RXD[7:0], RX_DV, RX_ER setup time to RX_CLK
RXD[7:0], RX_DV, RX_ER hold time to RX_CLK
RX_CLK clock rise time, (20% to 80%)
DD/2
and t
(GT) with respect to the t
the valid state (V) to state or setup time. Also, t
reference (K) going to the high state (H) relative to the time date input signals (D) going invalid (X) or hold time. Note that, in
general, the clock reference symbol representation is based on three letters representing the clock of a particular functional.
For example, the subscript of t
used with the appropriate letter: R (rise) or F (fall).
convention.
Refer to Errata QE_ENET18 in Chip Errata for the MPC8360E, Rev. 1 .
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4
(first two letters of functional block)(reference)(state)(signal)(state)
provides the GMII receive AC timing specifications.
shows the GMII transmit AC timing diagram.
GMII Receive AC Timing Specifications
Parameter/Condition
GTX_CLK
Parameter/Condition
TXD[7:0]
TX_EN
TX_ER
Table 27. GMII Transmit AC Timing Specifications (continued)
GTX
clock reference (K) going to the high state (H) relative to the time date input signals (D) reaching
GTX
Table 28. GMII Receive AC Timing Specifications
GTKHDX
Figure 10. GMII Transmit AC Timing Diagram
represents the GMII(G) transmit (TX) clock. For rise and fall times, the latter convention is
t
GTXH
DD
DD
/OV
minimum and t
/OV
DD
DD
t
GTX
of 3.3 V ± 10%.
of 3.3 V ± 10%.
GTKHDX
GTKHDV
symbolizes GMII transmit timing (GT) with respect to the t
for outputs. For example, t
t
G125H
Symbol
t
(first two letters of functional block)(signal)(state)(reference)(state)
GRXH
Symbol
t
t
t
GRDXKH
t
GRDVKH
maximum are not supported when the GTX_CLK is selected.
t
GTXF
t
G125
GTXF
t
GRXR
GRX
/t
/t
G125
t
GRX
GTKHDX
1
1
t
Min
Min
GTXR
2.0
0.2
45
40
—
—
—
—
GTKHDV
Typ
Typ
8.0
8.0
—
—
—
—
—
—
symbolizes GMII transmit timing
Max
Max
Freescale Semiconductor
1.0
1.0
—
55
—
60
—
—
Unit
Unit
ns
ns
ns
ns
ns
ns
%
%
GTX
for inputs
Notes
Notes
clock
—
—
—
—
—
2
2
2