DK-DEV-3CLS200N Altera, DK-DEV-3CLS200N Datasheet - Page 15

• Manufacturer Part Number: DK-DEV-3CLS200N
• Description: KIT DEV CYCLONE III LS EP3CLS200
• Manufacturer: Altera
• Series: Cyclone® IIIr
• Type: FPGAr

Specifications of DK-DEV-3CLS200N

• Contents: Board
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone
• Silicon Core Number: EP3C
• Silicon Family Name: Cyclone III LS
• Rohs Compliant: Yes
• For Use With/related Products: EP3CLS200
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2601

Chapter 1: Cyclone III Device Data Sheet
Switching Characteristics
Switching Characteristics
Core Performance Specifications
Table 1–20. Cyclone III Devices PLL Specifications
© January 2010 Altera Corporation
f
f
f
f
t
f
(2)
IN
INPF D
VC O
INDUTY
INJITTER_C CJ
OUT_EXT
(2)
(3)
(external clock output)
(4)
Symbol
This section provides the performance characteristics of the core and periphery blocks
for Cyclone III devices. All data is final and is based on actual silicon characterization
and testing. These numbers reflect the actual performance of the device under
worst-case silicon process, voltage, and junction temperature conditions.
Clock Tree Specifications
Table 1–19
Table 1–19. Cyclone III Devices Clock Tree Performance
PLL Specifications
Table 1–20
the commercial junction temperature range (0°C to 85°C), the industrial junction
temperature range (–40°C to 100°C), and the automotive junction temperature range
(–40°Cto 125°C). For more information about PLL block, refer to
“Glossary” on page
EP3C5
EP3C10
EP3C16
EP3C25
EP3C40
EP3C55
EP3C80
EP3C120
Note to
(1) EP3C120 offered in C7, C8, and I7 grades only.
Device
Table
Input clock frequency
PFD input frequency
PLL internal VCO operating range
Input clock duty cycle
Input clock cycle-to-cycle jitter
F
F
PLL output frequency
REF
REF
lists the clock tree specifications for Cyclone III devices.
describes the PLL specifications for Cyclone III devices when operating in
1–19:
≥ 100 MHz
< 100 MHz
1–27.
500
500
500
500
500
500
500
(1)
(Note 1)
C6
Parameter
(Part 1 of 2)
Performance
437.5
437.5
437.5
437.5
437.5
437.5
437.5
437.5
C7
Cyclone III Device Handbook, Volume 2
402
402
402
402
402
402
402
402
C8
Min
600
40
—
—
—
5
5
“PLL Block”
Typ
—
—
—
—
—
—
—
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Unit
472.5
472.5
1300
±750
Max
0.15
325
60
in
1–15
Unit
MHz
MHz
MHz
MHz
ps
%
UI