DK-DEV-3CLS200N Altera, DK-DEV-3CLS200N Datasheet - Page 28
DK-DEV-3CLS200N
Manufacturer Part Number
DK-DEV-3CLS200N
Description
KIT DEV CYCLONE III LS EP3CLS200
Manufacturer
Altera
Series
Cyclone® IIIr
Type
FPGAr
Datasheets
1.EP3C5F256C8N.pdf
(34 pages)
2.EP3C5F256C8N.pdf
(14 pages)
3.DK-START-3C25N.pdf
(74 pages)
4.DK-DEV-3CLS200N.pdf
(42 pages)
Specifications of DK-DEV-3CLS200N
Contents
Board
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Cyclone
Silicon Core Number
EP3C
Silicon Family Name
Cyclone III LS
Rohs Compliant
Yes
For Use With/related Products
EP3CLS200
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2601
1–28
Table 1–39. Glossary (Part 2 of 5)
Cyclone III Device Handbook, Volume 2
Letter
M
N
O
Q
K
L
P
J
JTAG Waveform
PLL Block
Term
—
—
—
—
—
—
Captured
The following block diagram highlights the PLL Specification parameters.
Core Clock
Driven
Signal
Signal
to be
to be
Key
TMS
CLK
TDO
TCK
TDI
Reconfigurable in User Mode
t
JCH
t
t
JSZX
JPZX
t
JCP
t
JSSU
t
JCL
Switchover
f
IN
t
JSH
N
t
t
JPCO
JSCO
t
t
f
INPFD
JPSU_TDI
JPSU_TMS
Definitions
PFD
—
—
—
—
—
—
M
CP
t
JSXZ
t
JPH
Phase tap
LF
Chapter 1: Cyclone III Device Data Sheet
VCO
© January 2010 Altera Corporation
t
JPXZ
f
VCO
Counters
C0..C4
CLKOUT Pins
f
f
OUT _EXT
OUT
Glossary
GCLK