DK-DEV-3CLS200N Altera, DK-DEV-3CLS200N Datasheet - Page 22

• Manufacturer Part Number: DK-DEV-3CLS200N
• Description: KIT DEV CYCLONE III LS EP3CLS200
• Manufacturer: Altera
• Series: Cyclone® IIIr
• Type: FPGAr

Specifications of DK-DEV-3CLS200N

• Contents: Board
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone
• Silicon Core Number: EP3C
• Silicon Family Name: Cyclone III LS
• Rohs Compliant: Yes
• For Use With/related Products: EP3CLS200
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2601

1–22
Cyclone III Device Handbook, Volume 2
Table 1–30. Cyclone III Devices Emulated LVDS Transmitter Timing Specifications
of 2)
Table 1–31. Cyclone III Devices LVDS Receiver Timing Specifications
TCCS
Output jitter
(peak to peak)
t
Notes to
(1) Emulated LVDS transmitter is supported at the output pin of all I/O banks.
(2) t
f
frequency)
HSIODR
SW
Input jitter
tolerance
t
Notes to
(1) LVDS receiver is supported at all banks.
(2) t
LOCK
HSC LK
LOCK
(2)
(2)
Symbol
Symbol
LOC K
(input clock
LOC K
Table
Table
is the time required for the PLL to lock from the end of device configuration.
is the time required for the PLL to lock from the end of device configuration.
1–30:
1–31:
Modes
Modes
×10
×10
×8
×7
×4
×2
×1
×8
×7
×4
×2
×1
—
—
—
—
—
—
Min
Min
100
10
10
10
10
10
10
80
70
40
20
10
—
—
—
—
—
—
C6
C6
437.5
437.5
437.5
437.5
437.5
437.5
437.5
Max
Max
875
875
875
875
875
400
500
200
500
1
1
Min
100
Min
10
10
10
10
10
10
80
70
40
20
10
—
—
—
—
—
—
C7, I7
C7, I7
Chapter 1: Cyclone III Device Data Sheet
402.5
402.5
Max
Max
370
370
370
370
370
740
740
740
740
740
400
500
200
500
1
1
© January 2010 Altera Corporation
(Note 1)
Min
Min
100
10
10
10
10
10
10
80
70
40
20
10
—
—
—
—
—
—
C8, A7
C8, A7
Switching Characteristics
(Note 1)
402.5
402.5
Max
Max
320
320
320
320
320
640
640
640
640
640
400
550
200
550
1
1
(Part 2
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
MHz
MHz
MHz
MHz
MHz
MHz
Unit
Unit
ms
ms
ps
ps
ps
ps