DK-DEV-3CLS200N Altera, DK-DEV-3CLS200N Datasheet - Page 34

KIT DEV CYCLONE III LS EP3CLS200

DK-DEV-3CLS200N

Manufacturer Part Number
DK-DEV-3CLS200N
Description
KIT DEV CYCLONE III LS EP3CLS200
Manufacturer
Altera
Series
Cyclone® IIIr
Type
FPGAr

Specifications of DK-DEV-3CLS200N

Contents
Board
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Cyclone
Silicon Core Number
EP3C
Silicon Family Name
Cyclone III LS
Rohs Compliant
Yes
For Use With/related Products
EP3CLS200
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2601
1–34
Table 1–40. Document Revision History
Cyclone III Device Handbook, Volume 2
May 2007
March 2007
Date
Version
1.1
1.0
(Part 3 of 3)
Initial release.
Corrected current unit in Tables 1-1, 1-12, and 1-14.
Added Note (3) to Table 1-3.
Updated Table 1-4 with I
Updated Table 1-9 and added Note (2).
Updated Table 1-19.
Updated Table 1-22 and added Note (1).
Changed I/O standard from 1.5-V LVTTL/LVCMOS and 1.2-V LVTTL/LVCMOS
to 1.5-V LVCMOS and 1.2-V LVCMOS in Tables 1-41, 1-42, 1-43, 1-44, and 1-
45.
Updated Table 1-43 with changes to LVPEC and LVDS and added Note (5).
Updated Tables 1-46, 1-47, Tables 1-54 through 1-95, and Tables 1-98
through 1-111.
Removed speed grade –6 from Tables 1-90 through 1-95, and from Tables 1-
110 through 1-111.
Added a waveform (Receiver Input Waveform) in glossary under letter “R”
(Table 1-112).
C CINT0
, I
Changes Made
CCA 0
, I
CCD_P LL0
, and I
Chapter 1: Cyclone III Device Data Sheet
C CIO0
© January 2010 Altera Corporation
information.
Document Revision History

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