DK-DEV-3CLS200N Altera, DK-DEV-3CLS200N Datasheet - Page 27

• Manufacturer Part Number: DK-DEV-3CLS200N
• Description: KIT DEV CYCLONE III LS EP3CLS200
• Manufacturer: Altera
• Series: Cyclone® IIIr
• Type: FPGAr

Specifications of DK-DEV-3CLS200N

• Contents: Board
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone
• Silicon Core Number: EP3C
• Silicon Family Name: Cyclone III LS
• Rohs Compliant: Yes
• For Use With/related Products: EP3CLS200
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2601

Chapter 1: Cyclone III Device Data Sheet
I/O Timing
I/O Timing
Glossary
Table 1–39. Glossary (Part 1 of 5)
© January 2010 Altera Corporation
Letter
D
G
H
A
B
C
E
F
I
f
GCLK
GCLK PLL
HSIODR
Input Waveforms
for the SSTL
Differential I/O
Standard
HS CLK
f
Term
—
—
—
—
—
You can use the following methods to determine the I/O timing:
■
■
The Excel-based I/O Timing provides pin timing performance for each device density
and speed grade. The data is typically used prior to designing the FPGA to get a
timing budget estimation as part of the link timing analysis. The Quartus II timing
analyzer provides a more accurate and precise I/O timing data based on the specifics
of the design after place-and-route is complete.
The Excel-based I/O Timing spreadsheet is downloadable from
Literature
Table 1–39
the Excel-based I/O Timing.
the Quartus II timing analyzer.
V
HIGH-SPEED I/O Block: High-speed receiver/transmitter input and output clock frequency.
Input pin directly to Global Clock network.
Input pin to Global Clock network through PLL.
HIGH-SPEED I/O Block: Maximum/minimum LVDS data transfer rate (HSIODR = 1/TUI).
SWING
website.
lists the glossary for this chapter.
Definitions
—
—
—
—
—
Cyclone III Device Handbook, Volume 2
Cyclone III Devices
V
V
V
REF
IH
IL
1–27