M37702E6BFS Renesas Electronics America, M37702E6BFS Datasheet - Page 179

• Manufacturer Part Number: M37702E6BFS
• Description: EPROM MCU/8BIT CMOS EMULATION CH
• Manufacturer: Renesas Electronics America

Specifications of M37702E6BFS

• Accessory Type: Emulator EPROM MCU
• For Use With/related Products: 7702
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Fig. 7.2.11 Block diagram of transfer clock generating section
Fig. 7.2.10 Structure of UARTi baud rate register (BRGi)
clock. It has a reload register. Assuming that a value set in the BRGi is “n” (n = “00
divides the count source frequency by n + 1.
of which frequency is the BRGi output’s frequency divided by 2 becomes the transfer clock. In the UART
mode, the BRGi is always valid, and a clock of which frequency is the BRGi output’s frequency divided by
16 becomes the transfer clock.
register whether transmission/reception is stopped or in progress. Accordingly, writing to their addresses,
perform it while that is stopped.
diagram of transfer clock generating section.
7.2.6 UARTi baud rate register (BRGi)
The UARTi baud rate register (BRGi) is an 8-bit timer exclusively used for UARTi to generate a transfer
In the clock synchronous serial I/O mode, the BRGi is valid when an internal clock is selected, and a clock
The data which is written to the addresses 31
Figure 7.2.10 shows the structure of the UARTi baud rate register (BRGi); Figure 7.2.11 shows the block
<Clock synchronous serial I/O mode>
<UART mode>
f
f
EXT
EXT
f
f
i
i
b7
BRGi
f
f
i
EXT
: Clock selected by BRG count source select bits (f
: Clock input to CLK
BRGi
1/2
b0
7702/7703 Group User’s Manual
i
UART0 baud rate register (Address 31
UART1 baud rate register (Address 39
pin (external clock)
1/16
1/16
7 to 0 Can be set to “00
Bit
16
Assuming that the set value = n, BRGi
divides the count source frequency by n + 1.
and 39
Transmit control circuit
Receive control circuit
Transmit control circuit
Receive control circuit
16
is written to both the timer register and the reload
Functions
16
” to “FF
2
, f
16
16
, f
.”
64
, or f
16
16
Transfer clock for transmit operation
Transfer clock for receive operation
Transfer clock for transmit operation
Transfer clock for receive operation
512
)
)
)
7.2 Block description
SERIAL I/O
Undefined
At reset
16
” to “FF
RW
WO
16
”), the BRGi
7–13