M37702E6BFS Renesas Electronics America, M37702E6BFS Datasheet - Page 401

• Manufacturer Part Number: M37702E6BFS
• Description: EPROM MCU/8BIT CMOS EMULATION CH
• Manufacturer: Renesas Electronics America

Specifications of M37702E6BFS

• Accessory Type: Emulator EPROM MCU
• For Use With/related Products: 7702
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 18.6.1 Calculation formulas and constants
18.6 Application
Some application examples of connecting external memorys for the low voltage version are described
bellow.
Applications shown here are just examples. Modify the desired application to suit the user’s need and make
sufficient evaluation before actually using it.
t
t
t
t
t
t
t
t
t
t
t
t
Note: For M37702E2LXXXGP and M37702E4LXXXFP,
Parameter
d(P0A-E)
d(P1A-E)
d(P2A-E)
w(EL)
su(P1D-E)
su(P2D-E)
d(E-P1Q)
d(E-P2Q)
pxz(E-P1Z)
pxz(E-P2Z)
pzx(E-P1Z)
pzx(E-P2Z)
18.6.1 Memory expansion
The following items of the low voltage version are the same as those of section “17.1 Memory expansion.”
However, a part of the formulas and constants for parameters is different.
•Memory expansion model
•Formulas for address access time of external memory
•Bus timing
•Memory expansion method
Table 18.6.1 lists the calculation formulas and constants for each parameter of the low voltage version.
Figure 18.6.1 shows the relationship between t
t
su(D)
refer to section “19.5.4 Bus timing and EPROM
mode.”
and f(X
t
time
address decode time
address latch delay time
t
t
t
t
a(AD)
(Note)
d(P0A/P1A/P2A–E)
su(P2D/P1D–E)
su(D)
d(E–P2Q/P1Q)
(Note)
f(X
Address access time of external memory t
Data setup time of external memory for writing data t
2
IN
)
= t
for each parameter (Unit : ns)
)
= t
IN
).
d(P0A/P1A/P2A–E)
w(EL)
2
f(X
No wait
: t
: t
– t
IN
10
d(E–P2Q)
su(P2D–E)
)
: t
d(E–P2Q/P1Q)
50 +
9
f(X
d(P0A–E)
– 40
1
1
IN
f(X
: time necessary for validating a chip select signal after an address is decoded
)
1
, or t
f(X
130
80
10
IN
10
, or t
+ t
2
)
8 MHz
, t
IN
10
(This is not necessary on the minimum model.)
9
: delay time necessary for latching an address
w(EL)
)
d(E–P1Q)
d(P1A–E)
4
9
– 30
su(P1D–E)
f(X
– 125
IN
7702/7703 Group User’s Manual
10
Wait
– t
)
9
su(P2D/P1D-E)
, or t
– 40
a(AD)
d(P2A–E)
and f(X
LOW VOLTAGE VERSION
a(AD)
– (address decode time
IN
). Figure 18.6.2 shows the relationship between
su(D)
1
+ address latch delay
18.6 Application
18–35