M37702E6BFS Renesas Electronics America, M37702E6BFS Datasheet - Page 76

• Manufacturer Part Number: M37702E6BFS
• Description: EPROM MCU/8BIT CMOS EMULATION CH
• Manufacturer: Renesas Electronics America

Specifications of M37702E6BFS

• Accessory Type: Emulator EPROM MCU
• For Use With/related Products: 7702
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

level sent from the preceding comparator (X in Figure 4.5.2); whichever interrupt of the higher priority level
is sent to the next comparator (Z in Figure 4.5.2). (Initial comparison value is “0.”) For interrupts for which
no interrupt request occurs, the priority level sent from the preceding comparator is forwarded to the next
comparator. When the two priority levels are found the same by comparison, the priority level sent from the
preceding comparator is forwarded to the next comparator. Accordingly, when the same priority level is set
by software, the interrupt requests are subject to the following relation about priority:
detectedd by the above comparison.
this interrupt priority level is higher than the processor interrupt priority level (IPL) and the interrupt disable
flag (I) is “0,” the interrupt request is accepted. A interrupt request which is not accepted here is retained
until it is accepted or its interrupt request bit is cleared to “0” by software.
cycle. However, when an op-code fetch cycle is generated during detection of an interrupt priority, new
detection of that does not start. (Refer to Figure 4.6.1.) Since the state of the interrupt request bit and
interrupt priority levels are latched during detection of interrupt priority, even if the bit state and priority
levels change, the detection is performed on the previous state before it has changed.
INTERRUPTS
4.5 Interrupt priority level detection circuit
The following explains the operation of the interrupt priority detection circuit using Figure 4.5.2.
The interrupt priority level of a requested interrupt (Y in Figure 4.5.2) is compared with the resultant priority
A-D conversion > UART1 transmit > UART1 receive > UART0 transmit > UART0 receive > Timer B2
Among the multiple interrupt requests sampled at the same time, one that has the highest priority level is
Then this highest interrupt priority level is compared with the processor interrupt priority level (IPL). When
The interrupt priority is detected when the CPU fetches an op code, which is called the CPU’s op-code fetch
Fig. 4.5.2 Interrupt priority level detection model
4–12
> Timer B1 > Timer B0 > Timer A4 > Timer A3 > Timer A2 > Timer A1 > Timer A0 > INT
Interrupt source Y
Y
Z
X
Comparator
(Priority level
comparison)
7702/7703 Group User’s Manual
Time
X : Resultant priority level sent from the preceding
Y : Priority level of interrupt source Y
Z : Highest priority at this point
comparator (Highest priority at this point)
When X
When X
Y then Z = X
Y then Z = Y
____
2
> INT
____
1
> INT
____
0