M37702E6BFS Renesas Electronics America, M37702E6BFS Datasheet - Page 78

• Manufacturer Part Number: M37702E6BFS
• Description: EPROM MCU/8BIT CMOS EMULATION CH
• Manufacturer: Renesas Electronics America

Specifications of M37702E6BFS

• Accessory Type: Emulator EPROM MCU
• For Use With/related Products: 7702
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

below.
is cleared to “0,” and then the interrupt processing starts from the next cycle of completion of the instruction
which is being executed at accepting the interrupt request. Figure 4.7.1 shows the sequence from acceptance
of interrupt request to execution of interrupt routine.
Acknowledge) sequence is executed, and a branch is made to the start address of the interrupt routine
allocated in addresses 0
INTACK sequence timing.
the INTACK sequence.
INTERRUPTS
4.7 Sequence from acceptance of interrupt request to execution of interrupt routine
4.7 Sequence from acceptance of interrupt request to execution of interrupt routine
The sequence from the acceptance of interrupt request to the execution of the interrupt routine is described
When an interrupt request is accepted, the interrupt request bit which corresponds to the accepted interrupt
After execution of an instruction at accepting the interrupt request is completed, an INTACK (Interrupt
The INTACK sequence is automatically performed in the following order.
Performing the INTACK sequence requires at least 13 cycles of internal clock . Figure 4.7.2 shows the
Execution is started beginning with an instruction at the start address of the interrupt routine after completing
4–14
The contents of the processor status register (PS) just before performing the INTACK sequence is stored
The contents of the program bank register (PG) just before performing the INTACK sequence are stored
The contents of the program counter (PC) just before performing the INTACK sequence are stored to
The interrupt disable flag (I) is set to “1.”
The interrupt priority level of the accepted interrupt is set into the processor interrupt priority level (IPL).
The contents of the program bank register (PG) are cleared to “00
to stack.
stack.
to stack.
vector address are set into the program counter (PC).
16
to FFFF
16
.
7702/7703 Group User’s Manual
16
,” and the contents of the interrupt