M37702E6BFS Renesas Electronics America, M37702E6BFS Datasheet - Page 67

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M37702E6BFS

Manufacturer Part Number
M37702E6BFS
Description
EPROM MCU/8BIT CMOS EMULATION CH
Manufacturer
Renesas Electronics America
Datasheet

Specifications of M37702E6BFS

Accessory Type
Emulator EPROM MCU
For Use With/related Products
7702
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M37702E6BFS
Manufacturer:
MITSUBISHI/三菱
Quantity:
20 000
When an interrupt request is accepted, the contents of the registers listed below immediately preceding the
acceptance of the interrupt request are automatically saved to the stack area in order of registers
Figure 4.1.2 shows the state of the stack area just before entering the interrupt routine.
Execute the RTI instruction at the end of this interrupt routine to return to the routine that the microcomputer
was executing before the interrupt request was accepted. As the RTI instruction is executed, the register
contents saved in the stack area are restored in order of registers
routine executed before the acceptance of interrupt request and processing is resumed from it.
When an interrupt request is accepted and the RTI instruction is executed, the only above registers
to be kept, use software to save and restore them.
Fig. 4.1.2 State of stack area just before entering interrupt routine
are automatically saved and restored. When there are any other registers of which contents are necessary
Program bank register (PG)
Program counter (PC
Processor status register (PS
[S] – 5
[S] – 4
[S] – 3
[S] – 2
[S] – 1
Address
[S]
[S] is an initial value that the stack pointer (S) indicates at
accepting an interrupt request. The S’s contents become
[S] – 5 after saving the above registers.
L
, PC
Processor status register’s high-order byte (PS
H
Processor status register’s low-order byte (PS
)
L
Program counter’s high-order byte (PC
, PS
Program counter’s low-order byte (PC
7702/7703 Group User’s Manual
H
)
Program bank register (PG)
Stack area
L
H
)
)
, and a return is made to the
L
H
)
INTERRUPTS
)
4.1 Overview
4–3
to
.

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