DSPIC30F1010-30I/SO Microchip Technology, DSPIC30F1010-30I/SO Datasheet - Page 91

IC DSPIC MCU/DSP 6K 28SOIC

DSPIC30F1010-30I/SO

Manufacturer Part Number
DSPIC30F1010-30I/SO
Description
IC DSPIC MCU/DSP 6K 28SOIC
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr

Specifications of DSPIC30F1010-30I/SO

Core Processor
dsPIC
Core Size
16-Bit
Speed
30 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
6KB (2K x 24)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Data Bus Width
16 bit
Processor Series
DSPIC30F
Core
dsPIC
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240002, DM300023, DM330011
Package
28SOIC W
Device Core
dsPIC
Family Name
dsPIC30
Maximum Speed
30 MHz
Operating Supply Voltage
3.3|5 V
Number Of Programmable I/os
21
Interface Type
I2C/SPI/UART
On-chip Adc
6-chx10-bit
Number Of Timers
2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM300023 - KIT DEMO DSPICDEM SMPS BUCKDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DSPIC30F1010-30I/SO
Manufacturer:
Microchip Technology
Quantity:
135
Part Number:
DSPIC30F1010-30I/SO
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
Company:
Part Number:
DSPIC30F1010-30I/SO
Quantity:
55
dsPIC30F1010/202X
8.4
Timer Interrupt
The 16-bit timer has the ability to generate an interrupt
on period match. When the timer count matches the
period register, the T1IF bit is asserted and an interrupt
will be generated, if enabled. The T1IF bit must be
cleared in software. The timer interrupt flag T1IF is
located in the IFS0 control register in the Interrupt
Controller.
When the Gated Time Accumulation mode is enabled,
an interrupt will also be generated on the falling edge of
the gate signal (at the end of the accumulation cycle).
Enabling an interrupt is accomplished via the respec-
tive timer interrupt enable bit, T1IE. The timer interrupt
enable bit is located in the IEC0 control register in the
Interrupt Controller.
Preliminary
© 2006 Microchip Technology Inc.
DS70178C-page 89

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