DSPIC30F4013-20I/PT Microchip Technology, DSPIC30F4013-20I/PT Datasheet - Page 107

• Manufacturer Part Number: DSPIC30F4013-20I/PT
• Description: IC DSPIC MCU/DSP 48K 44TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F4013-20I/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, I²S, POR, PWM, WDT
• Number Of I /o: 30
• Program Memory Size: 48KB (16K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 13x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of I/o's: 30
• Flash Memory Size: 48KB
• Supply Voltage Range: 2.5V To 5.5V
• Package: 44TQFP
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 30
• Interface Type: CAN/I2C/SPI/UART
• On-chip Adc: 13-chx12-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT44PT3 - SOCKET TRAN ICE 44MQFP/TQFPAC30F006 - MODULE SKT FOR DSPIC30F 44TQFPAC164305 - MODULE SKT FOR PM3 44TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: DSPIC30F401320IPT

16.5.2
The FERR bit (UxSTA<2>) is set if a ‘0’ is detected
instead of a Stop bit. If two Stop bits are selected, both
Stop bits must be ‘1’; otherwise, FERR is set. The read-
only FERR bit is buffered along with the received data;
it is cleared on any Reset.
16.5.3
The PERR bit (UxSTA<3>) is set if the parity of the
received word is incorrect. This error bit is applicable
only if a Parity mode (odd or even) is selected. The
read-only PERR bit is buffered along with the received
data bytes; it is cleared on any Reset.
16.5.4
When the receiver is active (i.e., between the initial
detection of the Start bit and the completion of the Stop
bit), the RIDLE bit (UxSTA<4>) is ‘0’. Between the com-
pletion of the Stop bit and detection of the next Start bit,
the RIDLE bit is ‘1’, indicating that the UART is Idle.
16.5.5
The receiver counts and expects a certain number of bit
times based on the values programmed in the PDSEL
(UxMODE<2:1>) and STSEL (UxMODE<0>) bits.
If the break is longer than 13 bit times, the reception is
considered complete after the number of bit times
specified by PDSEL and STSEL. The URXDA bit is set,
FERR is set, zeros are loaded into the receive FIFO,
interrupts are generated if appropriate, and the RIDLE
bit is set.
When the module receives a long Break signal and the
receiver has detected the Start bit, the data bits and the
invalid Stop bit (which sets the FERR), the receiver
must wait for a valid Stop bit before looking for the next
Start bit. It cannot assume that the Break condition on
the line is the next Start bit.
Break is regarded as a character containing all ‘0’s with
the FERR bit set. The Break character is loaded into
the buffer. No further reception can occur until a Stop bit
is received. Note that RIDLE goes high when the Stop
bit has not yet been received.
 2010 Microchip Technology Inc.
RECEIVE BREAK
FRAMING ERROR (FERR)
PARITY ERROR (PERR)
IDLE STATUS
16.6
Setting the ADDEN bit (UxSTA<5>) enables this
special mode in which a 9th bit (URX8) value of ‘1’
identifies the received word as an address, rather than
data. This mode is only applicable for 9-bit data
communication. The URXISEL control bit does not
have any impact on interrupt generation in this mode
since an interrupt (if enabled) is generated every time
the received word has the 9th bit set.
16.7
Setting the LPBACK bit enables this special mode in
which the UxTX pin is internally connected to the UxRX
pin. When configured for the Loopback mode, the
UxRX pin is disconnected from the internal UART
receive logic. However, the UxTX pin still functions as
in a normal operation.
To select this mode:
a)
b)
c)
16.8
The UART has a 16-bit Baud Rate Generator to allow
maximum flexibility in baud rate generation. The Baud
Rate Generator register (UxBRG) is readable and
writable. The baud rate is computed as follows:
BRG = 16-bit value held in UxBRG register
F
The Baud Rate is given by
EQUATION 16-1:
Therefore, the maximum baud rate possible is:
F
and the minimum baud rate possible is:
F
With a full 16-bit Baud Rate Generator at 30 MIPS
operation, the minimum baud rate achievable is
28.5 bps.
CY
CY
CY
dsPIC30F3014/4013
/16 (if BRG = 0),
/(16 * 65536).
Configure UART for desired mode of operation.
Set LPBACK = 1 to enable Loopback mode.
Enable transmission as defined in
“Transmitting
= Instruction Clock Rate (1/T
(0 through 65535)
Address Detect Mode
Loopback Mode
Baud Rate Generator
Baud Rate = F
Data”.
BAUD RATE
CY
Equation
/(16*(BRG+1))
CY
DS70138G-page 107
16-1.
)
Section 16.3