ATTINY25V-10MU Atmel, ATTINY25V-10MU Datasheet - Page 25

• Manufacturer Part Number: ATTINY25V-10MU
• Description: IC MCU AVR 2K FLASH 10MHZ 20-QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY25V-10MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 6
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-MLF®, QFN
• Processor Series: ATTINY2x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: USI
• Maximum Clock Frequency: 10 MHz
• Number Of Programmable I/os: 6
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 4-ch x 10-bit
• For Use With: ATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIPATAVRBC100 - REF DESIGN KIT BATTERY CHARGER770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.2
2586M–AVR–07/10
Clock Sources
In the ATtiny15 compatibility mode the frequency of the internal RC oscillator is calibrated down
to 6.4 MHz and the multiplication factor of the PLL is set to 4x. See
adjustments the clocking system is ATtiny15-compatible and the resulting fast peripheral clock
has a frequency of 25.6 MHz (same as in ATtiny15).
Figure 6-3.
Note that low speed mode is not implemented in ATtiny15 compatibility mode.
The device has the following clock source options, selectable by Flash Fuse bits as shown
below. The clock from the selected source is input to the AVR clock generator, and routed to the
appropriate modules.
Table 6-1.
Note:
The various choices for each clocking option is given in the following sections. When the CPU
wakes up from Power-down, the selected clock source is used to time the start-up, ensuring sta-
ble Oscillator operation before instruction execution starts. When the CPU starts from reset,
there is an additional delay allowing the power to reach a stable level before commencing nor-
Device Clocking Option
External Clock (see
High Frequency PLL Clock (see
Calibrated Internal Oscillator (see
Calibrated Internal Oscillator (see
Internal 128 kHz Oscillator (see
Low-Frequency Crystal Oscillator (see
Crystal Oscillator / Ceramic Resonator (see
Reserved
1. For all fuses “1” means unprogrammed while “0” means programmed.
2. The device is shipped with this option selected.
3. This will select ATtiny15 Compatibility Mode, where system clock is divided by four, resulting in
a 1.6 MHz clock frequency. For more inormation, see
27.
PCK Clocking System in ATtiny15 Compatibility Mode.
Device Clocking Options Select
OSCCAL
OSCILLATOR
page
6.4 MHz
26)
page
page
page
page
29)
26)
page
27)
27)
1/2
1/4
page
29)
3.2 MHz
1.6 MHz
30)
PLLE
PLL
8x
25.6 MHz
“Calibrated Internal Oscillator” on page
DETECTOR
LOCK
Figure
SYSTEM
CLOCK
PLOCK
CKSEL[3:0]
PCK
1000 – 1111
0101, 0111
0010
0011
6-3. With these
0000
0001
0100
0110
(2)
(3)
(1)
25