ATTINY25V-10MU Atmel, ATTINY25V-10MU Datasheet - Page 87

• Manufacturer Part Number: ATTINY25V-10MU
• Description: IC MCU AVR 2K FLASH 10MHZ 20-QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY25V-10MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 6
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-MLF®, QFN
• Processor Series: ATTINY2x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: USI
• Maximum Clock Frequency: 10 MHz
• Number Of Programmable I/os: 6
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 4-ch x 10-bit
• For Use With: ATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIPATAVRBC100 - REF DESIGN KIT BATTERY CHARGER770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2586M–AVR–07/10
Timer/Counter1 and the output compare registers serve as dual stand-alone PWMs with non-
overlapping non-inverted and inverted outputs. Refer to
this function. Similarly, the high prescaling opportunities make this unit useful for lower speed
functions or exact timing functions with infrequent actions.
Figure 12-2. Timer/Counter 1 Synchronization Register Block Diagram.
Timer/Counter1 and the prescaler allow running the CPU from any clock source while the pres-
caler is operating on the fast 64 MHz (or 32 MHz in Low Speed Mode) PCK clock in the
asynchronous mode.
Note that the system clock frequency must be lower than one third of the PCK frequency. The
synchronization mechanism of the asynchronous Timer/Counter1 needs at least two edges of
the PCK when the system clock is high. If the frequency of the system clock is too high, it is a
risk that data or control values are lost.
The following
PCKE
CK
PCK
SYNC
MODE
ASYNC
MODE
IO-registers
OCR1B
OCF1A
OCR1A
OCR1C
TCCR1
GTCCR
TCNT1
OCF1B
TOV1
Figure 12-3
1..2 PCK Delay
1/2 CK Delay
shows the block diagram for Timer/Counter1.
S
A
Input synchronization
registers
OCR1A_SI
OCR1B_SI
OCR1C_SI
TCCR1_SI
GTCCR_SI
TCNT1_SI
OCF1A_SI
OCF1B_SI
TOV1_SI
1 PCK Delay
1 CK Delay
S
A
8-BIT DATABUS
Timer/Counter1
TCNT1
page 89
~1 CK Delay
1 CK Delay
for a detailed description on
Output synchronization
registers
TCNT_SO
OCF1A_SO
OCF1B_SO
TOV1_SO
1/2 CK Delay
No Delay
TCNT1
OCF1A
OCF1B
TOV1
87