AT90PWM81-16MF Atmel, AT90PWM81-16MF Datasheet - Page 143

• Manufacturer Part Number: AT90PWM81-16MF
• Description: IC MCU AVR 8K FLASH ISP 32QFN
• Manufacturer: Atmel
• Series: AVR® 90PWM Lightingr

Specifications of AT90PWM81-16MF

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI
• Peripherals: Brown-out Detect/Reset, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 32-MLF®, QFN
• For Use With: ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12.26.2
7734P–AVR–08/10
PSC2 Interrupt Mask Register – PIM2
• Bit 4 – POMV2B0: Output Matrix Output B Ramp 0
This bit gives the state of the PSCOUT21 (and/or PSCOUT23) during ramp 0
• Bit 3 – POMV2A3: Output Matrix Output A Ramp 3
This bit gives the state of the PSCOUT20 (and/or PSCOUT22) during ramp 3
• Bit 2 – POMV2A2: Output Matrix Output A Ramp 2
This bit gives the state of the PSCOUT20 (and/or PSCOUT22) during ramp 2
• Bit 1 – POMV2A1: Output Matrix Output A Ramp 1
This bit gives the state of the PSCOUT20 (and/or PSCOUT22) during ramp 1
• Bit 0 – POMV2A0: Output Matrix Output A Ramp 0
This bit gives the state of the PSCOUT20 (and/or PSCOUT22) during ramp 0
Bit
Read/Write
Initial Value
• Bit 5 – PSEIEn : PSC n Synchro Error Interrupt Enable
When this bit is set, the PSEIn bit (if set) generate an interrupt.
• Bit 4 – PEVEnB : PSC n External Event B Interrupt Enable
When this bit is set, an external event which can generates a capture from Retrigger/Fault block B gener-
ates also an interrupt.
• Bit 3 – PEVEnA : PSC n External Event A Interrupt Enable
When this bit is set, an external event which can generates a capture from Retrigger/Fault block A gener-
ates also an interrupt.
• Bit 1– PEOEPEn : PSC n End Of Enhanced Cycle Interrupt Enable
When this bit is set, an interrupt is generated when PSC reaches the end of the 15th PSC cycle. This
allows to update the PSC values in the interrupt routine and to start a new enhanced cycle with the new
values at the next PSC cycle end.
• Bit 0 – PEOPEn : PSC n End Of Cycle Interrupt Enable
When this bit is set, an interrupt is generated when PSC reaches the end of the whole cycle.
7
-
R
0
6
-
R
0
5
PSEIE2
R/W
0
4
PEVE2B
R/W
0
3
PEVE2A
R/W
0
2
-
R
0
1
PEOEPE2 PEOPE2
R/W
0
AT90PWM81
0
R/W
0
PIM2
143