AT90PWM81-16MF Atmel, AT90PWM81-16MF Datasheet - Page 218

• Manufacturer Part Number: AT90PWM81-16MF
• Description: IC MCU AVR 8K FLASH ISP 32QFN
• Manufacturer: Atmel
• Series: AVR® 90PWM Lightingr

Specifications of AT90PWM81-16MF

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI
• Peripherals: Brown-out Detect/Reset, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 32-MLF®, QFN
• For Use With: ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17.8.2
218
AT90PWM81
ADC Control and Status Register A – ADCSRA
Table 17-4.
If these bits are changed during a conversion, the change will not take effect until this conversion is com-
plete (it means while the ADIF bit in ADCSRA register is set).
Bit
Read/Write
Initial Value
• Bit 7 – ADEN: ADC Enable Bit
Set this bit to enable the ADC.
Clear this bit to disable the ADC.
Clearing this bit while a conversion is running will take effect at the end of the conversion.
• Bit 6– ADSC: ADC Start Conversion Bit
Set this bit to start a conversion in single conversion mode or to start the first conversion in free running
mode.
Cleared by hardware when the conversion is complete. Writing this bit to zero has no effect.
The first conversion performs the initialization of the ADC.
• Bit 5 – ADATE: ADC Auto trigger Enable Bit
Set this bit to enable the auto triggering mode of the ADC.
Clear it to return in single conversion mode.
In auto trigger mode the trigger source is selected by the ADTS bits in the ADCSRB register. See
17-6 on page
• Bit 4– ADIF: ADC Interrupt Flag
Set by hardware as soon as a conversion is complete and the Data register are updated with the conversion
result.
Cleared by hardware when executing the corresponding interrupt handling vector.
Alternatively, ADIF can be cleared by writing it to logical one.
• Bit 3– ADIE: ADC Interrupt Enable Bit
Set this bit to activate the ADC end of conversion interrupt.
Clear it to disable the ADC end of conversion interrupt.
• Bit 2, 1, 0– ADPS2, ADPS1, ADPS0: ADC Prescaler Selection Bits
These 3 bits determine the division factor between the system clock frequency and input clock of the
ADC.
The different setting are shown in
MUX3
1
1
1
220.
7
ADEN
R/W
0
ADC Input Channel Selection
MUX2
1
1
1
6
ADSC
R/W
0
MUX1
0
1
1
Table 17-5 on page
R/W
5
ADATE
0
4
ADIF
R
0
MUX0
1
0
1
219.
3
ADIE
R/W
0
2
ADPS2
R/W
0
Description
VCC/4
Bandgap (Vbg)
GND
R/W
1
ADPS1
0
0
ADPS0
R/W
0
7734P–AVR–08/10
ADCSRA
Table