AT90PWM81-16MF Atmel, AT90PWM81-16MF Datasheet - Page 67

• Manufacturer Part Number: AT90PWM81-16MF
• Description: IC MCU AVR 8K FLASH ISP 32QFN
• Manufacturer: Atmel
• Series: AVR® 90PWM Lightingr

Specifications of AT90PWM81-16MF

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI
• Peripherals: Brown-out Detect/Reset, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 32-MLF®, QFN
• For Use With: ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.2
9.2.1
7734P–AVR–08/10
Ports as General Digital I/O
Configuring the Pin
The ports are bi-directional I/O ports with optional internal pull-ups.
description of one I/O-port pin, here generically called Pxn.
Figure 9-2.
Note:
Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in
tion for I/O-Ports” on page
the PORTx I/O address, and the PINxn bits at the PINx I/O address.
The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written logic one, Pxn is
configured as an output pin. If DDxn is written logic zero, Pxn is configured as an input pin.
If PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is activated.
To switch the pull-up resistor off, PORTxn has to be written logic zero or the pin has to be configured as
an output pin
The port pins are tri-stated when reset condition becomes active, even if no clocks are running.
1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk
Pxn
PUD are common to all ports.
General Digital I/O
SLEEP: SLEEP CONTROL
clk
PUD: PULLUP DISABLE
I/O
80, the DDxn bits are accessed at the DDRx I/O address, the PORTxn bits at
: I/O CLOCK
(1)
SLEEP
SYNCHRONIZER
WDx: WRITE DDRx
RDx: READ DDRx
WRx: WRITE PORTx
RRx: READ PORTx REGISTER
RPx: READ PORTx PIN
WPx: WRITE PINx REGISTER
D
L
Q
Q
D
PINxn
Figure 9-2
Q
Q
AT90PWM81
RESET
RESET
PORTxn
Q
Q
Q
Q
DDxn
CLR
CLR
D
D
shows a functional
RRx
“Register Descrip-
I/O
PUD
WDx
RDx
RPx
clk
, SLEEP, and
1
0
I/O
WPx
WRx
67