AT90PWM81-16MF Atmel, AT90PWM81-16MF Datasheet - Page 219

• Manufacturer Part Number: AT90PWM81-16MF
• Description: IC MCU AVR 8K FLASH ISP 32QFN
• Manufacturer: Atmel
• Series: AVR® 90PWM Lightingr

Specifications of AT90PWM81-16MF

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI
• Peripherals: Brown-out Detect/Reset, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 32-MLF®, QFN
• For Use With: ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17.8.3
7734P–AVR–08/10
ADC Control and Status Register B– ADCSRB
Table 17-5.
Bit
Read/Write
Initial Value
• Bit 7 – ADHSM: ADC High Speed Mode
Writing this bit to one enables the ADC High Speed mode. Set this bit if you wish to convert with an ADC
clock frequency higher than 200KHz.
• Bit 6 – ADNCDIS: ADC Noise Canceller Disable
Set this bit to disable automatic ADC start when entering Idle or ADC Noise reduction Modes.
Clear it to enable automatic ADC start when entering Idle or ADC reduction Modes..
The ADNCDIS must be set before entering Idle or ADC Noise reduction Modes if the ADC is running or
Auto triggered to prevent false ADC restart.
• Bit 5 – Reserved
• Bit 4 – ADSSEN: ADC Single Shot Enable on PSC’s synchronization signals
Set this bit to enable single shot mode when auto trigger on PSCRASY & PSC2ASY. In this case a single
conversion will be performed and PSCRASY & PSC2ASY will be blocked until ADCH reading.
Clear it to enable continuous conversion on PSCRASY & PSC2ASY auto triggering.
• Bit 3, 2, 1, 0– ADTS3:ADTS0: ADC Auto Trigger Source Selection Bits
These bits are only necessary in case the ADC works in auto trigger mode. It means if ADATE bit in
ADCSRA register is set.
In accordance with the Table 17-6, these 3 bits select the interrupt event which will generate the trigger of
the start of conversion. The start of conversion will be generated by the rising edge of the selected inter-
rupt flag whether the interrupt is enabled or not.
ADPS2
0
0
0
0
1
1
1
1
R/W
7
ADHSM
0
ADC Prescaler Selection
ADPS1
0
0
1
1
0
0
1
1
6
ADNCDIS
R/W
0
ADPS0
0
1
0
1
0
1
0
1
5
-
-
0
4
ADSSEN
R/W
0
Division Factor
2
2
4
8
16
32
64
128
3
ADTS3
R/W
0
2
ADTS2
R/W
0
1
R/W
0
ADTS1
AT90PWM81
0
ADTS0
R/W
0
ADCSRB
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