AT90PWM81-16MF Atmel, AT90PWM81-16MF Datasheet - Page 242

• Manufacturer Part Number: AT90PWM81-16MF
• Description: IC MCU AVR 8K FLASH ISP 32QFN
• Manufacturer: Atmel
• Series: AVR® 90PWM Lightingr

Specifications of AT90PWM81-16MF

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI
• Peripherals: Brown-out Detect/Reset, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 32-MLF®, QFN
• For Use With: ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

20.7.7
20.7.8
20.7.9
242
AT90PWM81
Setting the Boot Loader Lock Bits by SPM
EEPROM Write Prevents Writing to SPMCSR
Reading the Fuse and Lock Bits from Software
To set the Boot Loader Lock bits, write the desired data to R0, write “X0001001” to SPMCSR and exe-
cute SPM within four clock cycles after writing SPMCSR. The only accessible Lock bits are the Boot
Lock bits that may prevent the Application and Boot Loader section from any software update by the
MCU.
See
access.
If bits 5..2 in R0 are cleared (zero), the corresponding Boot Lock bit will be programmed if an SPM
instruction is executed within four cycles after BLBSET and SPMEN are set in SPMCSR. The Z-pointer
is don’t care during this operation, but for future compatibility it is recommended to load the Z-pointer
with 0x0001 (same as used for reading the lO
set bits 7, 6, 1, and 0 in R0 to “1” when writing the Lock bits. When programming the Lock bits the entire
Flash can be read during the operation.
Note that an EEPROM write operation will block all software programming to Flash. Reading the Fuses
and Lock bits from software will also be prevented during the EEPROM write operation. It is recom-
mended that the user checks the status bit (EEPE) in the EECR Register and verifies that the bit is cleared
before writing to the SPMCSR Register.
It is possible to read both the Fuse and Lock bits from software. To read the Lock bits, load the Z-pointer
with 0x0001 and set the BLBSET and SPMEN bits in SPMCSR. When an LPM instruction is executed
within three CPU cycles after the BLBSET and SPMEN bits are set in SPMCSR, the value of the Lock
bits will be loaded in the destination register. The BLBSET and SPMEN bits will auto-clear upon comple-
tion of reading the Lock bits or if no LPM instruction is executed within three CPU cycles or no SPM
instruction is executed within four CPU cycles. When BLBSET and SPMEN are cleared, LPM will work
as described in the Instruction set Manual.
The algorithm for reading the Fuse Low byte is similar to the one described above for reading the Lock
bits. To read the Fuse Low byte, load the Z-pointer with 0x0000 and set the BLBSET and SPMEN bits in
SPMCSR. When an LPM instruction is executed within three cycles after the BLBSET and SPMEN bits
are set in the SPMCSR, the value of the Fuse Low byte (FLB) will be loaded in the destination register as
shown below. Refer to
byte.
Similarly, when reading the Fuse High byte, load 0x0003 in the Z-pointer. When an LPM instruction is
executed within three cycles after the BLBSET and SPMEN bits are set in the SPMCSR, the value of the
Fuse High byte (FHB) will be loaded in the destination register as shown below. Refer to
page 251
Bit
R0
Bit
Rd
Bit
Rd
Bit
Rd
Table 20-2
for detailed description and mapping of the Fuse High byte.
7
1
7
–
7
FLB7
7
FHB7
and
Table 20-3
Table 21-4 on page 249
6
1
6
–
6
FLB6
6
FHB6
for how the different settings of the Boot Loader bits affect the Flash
5
BLB12
5
BLB12
5
FLB5
5
FHB5
ck
4
FLB4
4
FHB4
4
BLB11
4
BLB11
bits). For future compatibility it is also recommended to
for a detailed description and mapping of the Fuse Low
3
BLB02
3
BLB02
3
FLB3
3
FHB3
2
BLB01
2
BLB01
2
FLB2
2
FHB2
1
1
1
LB2
1
FLB1
1
FHB1
0
1
0
LB1
0
FLB0
0
FHB0
7734P–AVR–08/10
Table 21-5 on