AT90PWM81-16MF Atmel, AT90PWM81-16MF Datasheet - Page 185

• Manufacturer Part Number: AT90PWM81-16MF
• Description: IC MCU AVR 8K FLASH ISP 32QFN
• Manufacturer: Atmel
• Series: AVR® 90PWM Lightingr

Specifications of AT90PWM81-16MF

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI
• Peripherals: Brown-out Detect/Reset, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 32-MLF®, QFN
• For Use With: ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.3.2
14.4
7734P–AVR–08/10
Data Modes
Master Mode
The SS pin is useful for packet/byte synchronization to keep the slave bit counter synchronous with the
master clock generator. When the SS pin is driven high, the SPI slave will immediately reset the send and
receive logic, and drop any partially received data in the Shift Register.
When the SPI is configured as a Master (MSTR in SPCR is set), the user can determine the direction of
the SS pin.
If SS is configured as an output, the pin is a general output pin which does not affect the SPI system. Typ-
ically, the pin will be driving the SS pin of the SPI Slave.
If SS is configured as an input, it must be held high to ensure Master SPI operation. If the SS pin is driven
low by peripheral circuitry when the SPI is configured as a Master with the SS pin defined as an input, the
SPI system interprets this as another master selecting the SPI as a slave and starting to send data to it. To
avoid bus contention, the SPI system takes the following actions:
Thus, when interrupt-driven SPI transmission is used in Master mode, and there exists a possibility that SS
is driven low, the interrupt should always check that the MSTR bit is still set. If the MSTR bit has been
cleared by a slave select, it must be set by the user to re-enable SPI Master mode.
There are four combinations of SCK phase and polarity with respect to serial data, which are determined
by control bits CPHA and CPOL. The SPI data transfer formats are shown in
Data bits are shifted out and latched in on opposite edges of the SCK signal, ensuring sufficient time for
data signals to stabilize. This is clearly seen by summarizing
Table 14-2.
1.
2.
The MSTR bit in SPCR is cleared and the SPI system becomes a Slave. As a result of the SPI
becoming a Slave, the MOSI and SCK pins become inputs.
The SPIF flag in SPSR is set, and if the SPI interrupt is enabled, and the I-bit in SREG is set, the
interrupt routine will be executed.
CPOL=0, CPHA=0
CPOL=0, CPHA=1
CPOL=1, CPHA=0
CPOL=1, CPHA=1
CPOL Functionality
Sample (Falling)
Sample (Rising)
Setup (Falling)
Leading Edge
Setup (Rising)
Table 14-3
Sample (Falling)
Sample (Rising)
Setup (Falling)
Setup (Rising)
Trailing eDge
and
Table
Figure 14-3
AT90PWM81
14-4, as done below:
and
SPI Mode
Figure
0
1
2
3
14-4.
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