AT90PWM81-16MF Atmel, AT90PWM81-16MF Datasheet - Page 187

• Manufacturer Part Number: AT90PWM81-16MF
• Description: IC MCU AVR 8K FLASH ISP 32QFN
• Manufacturer: Atmel
• Series: AVR® 90PWM Lightingr

Specifications of AT90PWM81-16MF

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI
• Peripherals: Brown-out Detect/Reset, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 32-MLF®, QFN
• For Use With: ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7734P–AVR–08/10
• Bit 5 – DORD: Data Order
When the DORD bit is written to one, the LSB of the data word is transmitted first.
When the DORD bit is written to zero, the MSB of the data word is transmitted first.
• Bit 4 – MSTR: Master/Slave Select
This bit selects Master SPI mode when written to one, and Slave SPI mode when written logic zero. If SS
is configured as an input and is driven low while MSTR is set, MSTR will be cleared, and SPIF in SPSR
will become set. The user will then have to set MSTR to re-enable SPI Master mode.
• Bit 3 – CPOL: Clock Polarity
When this bit is written to one, SCK is high when idle. When CPOL is written to zero, SCK is low when
idle. Refer to
Table 14-3.
• Bit 2 – CPHA: Clock Phase
The settings of the Clock Phase bit (CPHA) determine if data is sampled on the leading (first) or trailing
(last) edge of SCK. Refer to
marized below:
Table 14-4.
• Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0
These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have no effect
on the Slave. The relationship between SCK and the clk
Table 14-5.
SPI2X
0
0
0
0
1
1
1
1
Figure 14-3
CPOL
CPHA
CPOL Functionality
CPHA Functionality
Relationship Between SCK and the Oscillator Frequency
0
1
0
1
and
Figure 14-3
SPR1
Figure 14-4
0
0
1
1
0
0
1
1
and
for an example. The CPOL functionality is summarized below:
Leading Edge
Leading Edge
Figure 14-4
Sample
Falling
Rising
Setup
SPR0
0
1
0
1
0
1
0
1
IO
for an example. The CPOL functionality is sum-
frequency f
SCK Frequency
f
f
f
f
f
f
f
f
clkio
clkio
clkio
clkio
clkio
clkio
clkio
clkio
/
/
/
/
/
/
/
/
4
16
64
128
2
8
32
64
clkio
is shown in the following table:
AT90PWM81
Trailing Edge
Trailing Edge
Sample
Falling
Rising
Setup
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