PIC18LF25K22-I/SP Microchip Technology, PIC18LF25K22-I/SP Datasheet - Page 292

• Manufacturer Part Number: PIC18LF25K22-I/SP
• Description: MCU 8BIT 32KB FLASH 3.6V 28SDIP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18LF25K22-I/SP

• Program Memory Type: FLASH
• Program Memory Size: 32KB (16K x 16)
• Package / Case: 28-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 24
• Eeprom Size: 256 x 8
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 19x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1536 B
• Interface Type: I2C, SPI, EUSART
• Maximum Clock Frequency: 64 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 7
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164005
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 17 Channel
• On-chip Dac: 5 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC18(L)F2X/4XK22
17.1
When configuring and using the ADC the following
functions must be considered:
• Port configuration
• Channel selection
• ADC voltage reference selection
• ADC conversion clock source
• Interrupt control
• Results formatting
17.1.1
The ANSELx and TRISx registers configure the A/D
port pins. Any port pin needed as an analog input
should have its corresponding ANSx bit set to disable
the digital input buffer and TRISx bit set to disable the
digital output driver. If the TRISx bit is cleared, the
digital output level (V
The A/D operation is independent of the state of the
ANSx bits and the TRIS bits.
17.1.2
The CHS bits of the ADCON0 register determine which
channel is connected to the sample and hold circuit.
When changing channels, a delay is required before
starting the next conversion. Refer to
“ADC Operation”
DS41412D-page 292
Note 1: When reading the PORT register, all pins
2: Analog levels on any pin with the corre-
3: The
ADC Configuration
PORT CONFIGURATION
CHANNEL SELECTION
with their corresponding ANSx bit set
read as cleared (a low level). However,
analog conversion of pins configured as
digital inputs (ANSx bit cleared and
TRISx
converted.
sponding ANSx bit cleared may cause
the digital input buffer to consume current
out of the device’s specification limits.
Register 3H configures PORTB pins to
reset as analog or digital pins by
controlling how the bits in ANSELB are
reset.
PBADEN
for more information.
OH
bit
or V
set)
OL
) will be converted.
bit
will
in
be
Configuration
Section 17.2
accurately
Preliminary
17.1.3
The PVCFG<1:0> and NVCFG<1:0> bits of the
ADCON1 register provide independent control of the
positive and negative voltage references.
The positive voltage reference can be:
• V
• the fixed voltage reference (FVR BUF2)
• an external voltage source (V
The negative voltage reference can be:
• V
• an external voltage source (V
17.1.4
The ADCON2 register allows the user to select an
acquisition time that occurs each time the GO/DONE
bit is set.
Acquisition time is set with the ACQT<2:0> bits of the
ADCON2 register. Acquisition delays cover a range of
2 to 20 T
module continues to sample the input for the selected
acquisition
conversion. Since the acquisition time is programmed,
there is no need to wait for an acquisition time between
selecting a channel and setting the GO/DONE bit.
Manual
ACQT<2:0> = 000. When the GO/DONE bit is set,
sampling is stopped and a conversion begins. The user
is responsible for ensuring the required acquisition time
has passed between selecting the desired input
channel and setting the GO/DONE bit. This option is
also the default Reset state of the ACQT<2:0> bits and
is compatible with devices that do not offer
programmable acquisition times.
In either case, when the conversion is completed, the
GO/DONE bit is cleared, the ADIF flag is set and the
A/D begins sampling the currently selected channel
again. When an acquisition time is programmed, there
is no indication of when the acquisition time ends and
the conversion begins.
DD
SS
AD
ADC V
SELECTING AND CONFIGURING
ACQUISITION TIME
. When the GO/DONE bit is set, the A/D
acquisition
time,
OLTAGE REFERENCE
then
 2010 Microchip Technology Inc.
automatically
is
REF
REF
selected
-)
+)
begins
when
a