MCU AVR 8K FLASH 16MHZ 28-PDIP

ATMEGA8A-PU

Manufacturer Part NumberATMEGA8A-PU
DescriptionMCU AVR 8K FLASH 16MHZ 28-PDIP
ManufacturerAtmel
SeriesAVR® ATmega
ATMEGA8A-PU datasheets
 

Specifications of ATMEGA8A-PU

Core ProcessorAVRCore Size8-Bit
Speed16MHzConnectivityI²C, SPI, UART/USART
PeripheralsBrown-out Detect/Reset, POR, PWM, WDTNumber Of I /o23
Program Memory Size8KB (4K x 16)Program Memory TypeFLASH
Eeprom Size512 x 8Ram Size1K x 8
Voltage - Supply (vcc/vdd)2.7 V ~ 5.5 VData ConvertersA/D 6x10b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case28-DIP (0.300", 7.62mm)Processor SeriesATMEGA8x
CoreAVR8Data Bus Width8 bit
Data Ram Size1 KBInterface TypeSPI, TWI, USART
Maximum Clock Frequency16 MHzNumber Of Programmable I/os23
Number Of Timers3Maximum Operating Temperature+ 85 C
Mounting StyleThrough Hole3rd Party Development ToolsEWAVR, EWAVR-BL
Development Tools By SupplierATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKITMinimum Operating Temperature- 40 C
On-chip Adc10 bit, 6 ChannelPackage28PDIP
Device CoreAVRFamily NameATmega
Maximum Speed16 MHzOperating Supply Voltage3.3|5 V
Controller Family/seriesAVR MEGANo. Of I/o's23
Eeprom Memory Size512ByteRam Memory Size1KB
Cpu Speed16MHzRohs CompliantYes
For Use WithATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KITLead Free Status / RoHS StatusLead free / RoHS Compliant
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Features
High-performance, Low-power Atmel
Advanced RISC Architecture
– 130 Powerful Instructions – Most Single-clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 16MIPS Throughput at 16MHz
– On-chip 2-cycle Multiplier
High Endurance Non-volatile Memory segments
– 8KBytes of In-System Self-programmable Flash program memory
– 512Bytes EEPROM
– 1KByte Internal SRAM
– Write/Erase Cycles: 10,000 Flash/100,000 EEPROM
– Data retention: 20 years at 85°C/100 years at 25°C
– Optional Boot Code Section with Independent Lock Bits
• In-System Programming by On-chip Boot Program
• True Read-While-Write Operation
– Programming Lock for Software Security
Peripheral Features
– Two 8-bit Timer/Counters with Separate Prescaler, one Compare Mode
– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture
Mode
– Real Time Counter with Separate Oscillator
– Three PWM Channels
– 8-channel ADC in TQFP and QFN/MLF package
• Eight Channels 10-bit Accuracy
– 6-channel ADC in PDIP package
• Six Channels 10-bit Accuracy
– Byte-oriented Two-wire Serial Interface
– Programmable Serial USART
– Master/Slave SPI Serial Interface
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
Special Microcontroller Features
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated RC Oscillator
– External and Internal Interrupt Sources
– Five Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, and
Standby
I/O and Packages
– 23 Programmable I/O Lines
– 28-lead PDIP, 32-lead TQFP, and 32-pad QFN/MLF
Operating Voltages
– 2.7 - 5.5V
– 0 - 16MHz
Power Consumption at 4MHz, 3V, 25°C
– Active: 3.6mA
– Idle Mode: 1.0mA
– Power-down Mode: 0.5µA
®
®
AVR
8-bit Microcontroller
(1)
8-bit
with 8KBytes
In-System
Programmable
Flash
ATmega8A
8159D–AVR–02/11

ATMEGA8A-PU Summary of contents

  • Page 1

    ... Operating Voltages – 2.7 - 5.5V – 16MHz • Power Consumption at 4MHz, 3V, 25°C – Active: 3.6mA – Idle Mode: 1.0mA – Power-down Mode: 0.5µA ® ® AVR 8-bit Microcontroller (1) 8-bit with 8KBytes In-System Programmable Flash ATmega8A 8159D–AVR–02/11 ...

  • Page 2

    ... Pin Configurations Figure 1-1. 8159D–AVR–02/11 Pinout ATmega8A PDIP (RESET) PC6 1 28 (RXD) PD0 2 27 (TXD) PD1 3 26 (INT0) PD2 4 25 (INT1) PD3 5 24 (XCK/T0) PD4 6 23 VCC 7 22 GND 8 21 (XTAL1/TOSC1) PB6 9 20 (XTAL2/TOSC2) PB7 10 19 (T1) PD5 11 18 (AIN0) PD6 ...

  • Page 3

    ... Overview The Atmel RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega8A achieves throughputs approaching 1 MIPS per MHz, allowing the system designer to optimize power consumption versus processing speed. 2.1 Block Diagram Figure 2-1. 8159D–AVR–02/11 ® ® AVR ...

  • Page 4

    ... RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega8A is a powerful microcontroller that provides a highly-flexible and cost-effective solu- tion to many embedded control applications. The Atmel AVR ATmega8A is supported with a full suite of program and system development tools, including C compilers, macro assemblers, program debugger/simulators, In-Circuit Emula- tors, and evaluation kits. ...

  • Page 5

    ... As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port D also serves the functions of various special features of the ATmega8A as listed on 63. 2.2.7 RESET Reset input ...

  • Page 6

    ... These code examples assume that the part specific header file is included before compi- lation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling compiler dependent. Please confirm with the C compiler documentation for more details. 8159D–AVR–02/11 1. ATmega8A 6 ...

  • Page 7

    ... AVR core architecture in general. The main function of the Block Diagram of the AVR MCU Architecture Program Flash Counter Program Memory Instruction Register Instruction Decoder Control Lines ATmega8A Data Bus 8-bit Status and Control Interrupt Unit General Purpose SPI Registrers Unit Watchdog Timer ...

  • Page 8

    ... The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software. 8159D–AVR–02/11 ® ® AVR ALU operates in direct connection with all the 32 general ATmega8A 8 ...

  • Page 9

    ... Set Description” for detailed information. • Bit 0 – C: Carry Flag The Carry Flag C indicates a Carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. 8159D–AVR–02/ R/W R/W R/W R ⊕ V ATmega8A R/W R/W R/W R SREG 9 ...

  • Page 10

    ... R15 Working R16 Registers R17 … R26 R27 R28 R29 R30 R31 Figure 6-2, each register is also assigned a Data memory address, mapping them ATmega8A ® ® AVR Enhanced RISC instruction set. In order to 0 Addr. 0x00 0x01 0x02 0x0D 0x0E 0x0F 0x10 ...

  • Page 11

    ... Incremented by 1 Data is popped from the stack Incremented by 2 Return address is popped from the stack with return from subroutine or return from interrupt ® ® AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The num- ATmega8A Figure 6- R26 (0x1A ...

  • Page 12

    ... Instruction Fetch 3rd Instruction Fetch 4th Instruction Fetch shows the internal timing concept for the Register File single clock cycle an ALU Single Cycle ALU Operation T1 clk CPU Total Execution Time Result Write Back ATmega8A SP12 SP11 SP10 SP9 SP4 SP3 ...

  • Page 13

    ... AVR provides several different interrupt sources. These interrupts and the separate for details. for more information. The Reset Vector can also be moved to the start of 212. ATmega8A “Interrupts” on page 45. The list also “Boot Loader Support – Read- 13 ...

  • Page 14

    ... Program Counter (2 bytes) is popped back from the Stack, the Stack Pointer is incre- mented by 2, and the I-bit in SREG is set. 8159D–AVR–02/11 ; store SREG value ; disable interrupts during timed sequence ; start EEPROM write ; restore SREG value (I-bit) ; set global interrupt enable ATmega8A ® ® AVR interrupts is four clock cycles 14 ...

  • Page 15

    ... For software security, the Flash Program memory space is divided into two sections, Boot Program section and Application Program section. The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATmega8A Pro- gram Counter (PC bits wide, thus addressing the 4K Program memory locations. The ...

  • Page 16

    ... When using register indirect addressing modes with automatic pre-decrement and post-incre- ment, the address registers X, Y and Z are decremented or incremented. The 32 general purpose working registers, 64 I/O Registers, and the 1024 bytes of internal data SRAM in the ATmega8A are all accessible through all these addressing modes. The Register File is described in 8159D–AVR–02/11 ...

  • Page 17

    ... I/O Registers $00 $01 $02 ... $3D $3E $3F On-chip Data SRAM Access Cycles T1 clk CPU Address Compute Address Data WR Data RD Memory Vccess Instruction ATmega8A Data Address Space $0000 $0001 $0002 ... $001D $001E $001F $0020 $0021 $0022 ... $005D $005E $005F Internal SRAM $0060 $0061 ... ...

  • Page 18

    ... I/O Memory The I/O space definition of the ATmega8A is shown in All ATmega8A I/Os and peripherals are placed in the I/O space. The I/O locations are accessed by the IN and OUT instructions, transferring data between the 32 general purpose working regis- ters and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit- accessible using the SBI and CBI instructions ...

  • Page 19

    ... Initial Value • Bits 15:9 – Res: Reserved Bits These bits are reserved bits in the ATmega8A and will always read as zero. • Bits 8:0 – EEAR8:0: EEPROM Address The EEPROM Address Registers – EEARH and EEARL – specify the EEPROM address in the 512 bytes EEPROM space ...

  • Page 20

    ... Figure 7-4. Symbol EEPROM Write (from CPU) Note: 8159D–AVR–02/11 EEPROM Programming Time Number of Calibrated RC Oscillator 1. Uses 1MHz clock, independent of CKSEL Fuse settings. ATmega8A for details about boot Table 7-4 lists the typical pro- (1) Cycles Typ Programming Time 8448 “Boot Loader 8 ...

  • Page 21

    ... Start eeprom write by setting EEWE sbi EECR,EEWE ret /* Wait for completion of previous write */ while(EECR & (1<<EEWE Set up address and data registers */ EEAR = uiAddress; EEDR = ucData; /* Write logical one to EEMWE */ EECR |= (1<<EEMWE); /* Start eeprom write by setting EEWE */ EECR |= (1<<EEWE); ATmega8A 21 ...

  • Page 22

    ... Wait for completion of previous write */ while(EECR & (1<<EEWE Set up address register */ EEAR = uiAddress; /* Start eeprom read by writing EERE */ EECR |= (1<<EERE); /* Return data from data register */ return EEDR; the EEPROM data can be corrupted because the supply voltage is CC, ATmega8A 22 ...

  • Page 23

    ... Brown-out Detector (BOD). If the detection level of the internal BOD does not match the needed detection level, an external low V tion circuit can be used reset occurs while a write operation is in progress, the write operation will be completed provided that the power supply voltage is sufficient. 8159D–AVR–02/11 ATmega8A Reset Protec ...

  • Page 24

    ... AVR Clock I/O Control Unit clk ASY Clock Multiplexer External RC Oscillator Oscillator External Clock is halted, enabling TWI address reception in all sleep modes. I/O ATmega8A Figure 8-1. CPU Core RAM clk ADC clk CPU clk FLASH Reset Logic Watchdog Timer Source Clock ...

  • Page 25

    ... ASY Device Clocking Options Select 1. For all fuses “1” means unprogrammed while “0” means programmed. Number of Watchdog Oscillator Cycles = 5.0V) Typical Time-out ( ATmega8A (1) CKSEL3:0 1111 - 1010 1000 - 0101 0100 - 0001 “Typical Charac- = 3.0V) Number of Cycles CC 4 ...

  • Page 26

    ... This option should not be used with crystals, only with ceramic resonators. ATmega8A Figure 8-2. Either a quartz crystal or a Table 8-3. For ceramic resonators, the XTAL2 XTAL1 GND Table 8-3 ...

  • Page 27

    ... Additional Delay Power-down and from Reset Power-save ( 32K CK 1. These options should only be used if frequency stability at start-up is not important for the application. ATmega8A Additional Delay from Reset (V = 5.0V) Recommended Usage CC Ceramic resonator, fast rising 4.1 ms power Ceramic resonator, slowly 65 ms rising power Ceramic resonator, BOD – ...

  • Page 28

    ... Start-up Time from Additional Delay Power-down and from Reset Power-save ( ( This option should not be used when operating close to the maximum frequency of the device. ATmega8A NC XTAL2 XTAL1 GND Table Frequency Range (MHz) 0.1 - 0.9 0.9 - 3.0 3.0 - 8.0 8.0 - 12.0 = 5.0V) Recommended Usage CC – ...

  • Page 29

    ... Start-up Times for the Internal Calibrated RC Oscillator Clock Selection Start-up Time from Power-down and Power- save The device is shipped with this option selected. ATmega8A Table 8-8. If selected, it will operate with no exter- and Temperature. When this Oscillator is used CC Nominal Frequency (MHz) 1.0 2.0 4 ...

  • Page 30

    ... Start-up Times for the External Clock Selection Start-up Time from Power-down and Power-save The Timer/Counter Oscillator uses the same type of crystal oscillator as Low-Frequency Oscillator and the internal capacitors have the same nominal value of 36 pF. ATmega8A Additional Delay from Reset (V = 5.0V) Recommended Usage CC – BOD enabled 4 ...

  • Page 31

    ... CAL7 CAL6 CAL5 R/W R/W R/W Device Specific Calibration Value Table Internal RC Oscillator Frequency Range Min Frequency in Percentage of Nominal Frequency (%) 0x00 50 0x7F 75 0xFF 100 ATmega8A CAL4 CAL3 CAL2 CAL1 R/W R/W R/W R/W 8-11. Max Frequency in Percentage of Nominal Frequency (%) 100 150 ...

  • Page 32

    ... MCU wakes up and executes from the Reset Vector. Note that the Extended Standby mode present in many other AVR MCUs has been removed in the ATmega8A, as the TOSC and XTAL inputs share the same physical pins. 8159D–AVR–02/11 presents the different clock systems in the ATmega8A, and their distribu- ...

  • Page 33

    ... Timer/Counter2 will run during sleep. The device can wake up from either Timer Overflow or 8159D–AVR–02/11 and clk , while allowing the other clocks to run. CPU FLASH “Clock Sources” on page ATmega8A , clk , and clk , while allowing I/O CPU FLASH “External Interrupts” on page 67 25 ...

  • Page 34

    ... If the 8159D–AVR–02/11 , allowing operation only of asynchronous ASY “Analog-to-Digital Converter” on page 198 “Analog Comparator” on page 195 “Brown-out Detection” on page 39 ATmega8A for details on how to for details on how to 34 ...

  • Page 35

    ... Timer” on page 41 for details on how to configure the Watchdog Timer. ) and the ADC clock (clk I/O “Digital Input Enable and Sleep Modes” on page 54 /2, the input buffer will use excessive power. CC ATmega8A “Internal Volt- ) are stopped, the input buffers of the ADC for 35 ...

  • Page 36

    ... SM2 SM1 R/W R/W R Sleep Mode Select SM1 SM0 Standby mode is only available with external crystals or resonators. ATmega8A SM0 ISC11 ISC10 ISC01 R/W R/W R/W R Table Sleep Mode Idle ADC Noise Reduction Power-down Power-save Reserved Reserved (1) Standby 0 ISC00 MCUCR R/W 0 9-2. ...

  • Page 37

    ... Reset Sources The ATmega8A has four sources of Reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V • External Reset. The MCU is reset when a low level is present on the RESET pin for longer than the minimum pulse length. • ...

  • Page 38

    ... Table 25-3 on page 247. The POR is activated whenever V rise. The RESET signal is activated again, without any delay, CC decreases below the detection level POT RST RESET t TOUT RESET ATmega8A DATA BUS MCU Control and Status Register (MCUCSR) Delay Counters CK TIMEOUT is below the detection ...

  • Page 39

    ... Figure 10-4. External Reset During Operation 10.2.3 Brown-out Detection ATmega8A has an On-chip Brown-out Detection (BOD) circuit for monitoring the V ing operation by comparing fixed trigger level. The trigger level for the BOD can be selected by the fuse BODLEVEL to be 2.7V (BODLEVEL unprogrammed), or 4.0V (BODLEVEL programmed) ...

  • Page 40

    ... Figure 10-6. Watchdog Reset During Operation 10.3 Internal Voltage Reference ATmega8A features an internal bandgap reference. This reference is used for Brown-out Detec- tion, and it can be used as an input to the Analog Comparator or the ADC. The 2.56V reference to the ADC is generated from the internal bandgap reference. ...

  • Page 41

    ... Timer. The Watchdog Timer is also reset when it is disabled and when a Chip Reset occurs. Eight different clock cycle periods can be selected to determine the reset period. If the reset period expires without another Watchdog Reset, the ATmega8A resets and executes from the Reset Vector. For timing details on the Watchdog Reset, refer to To prevent unintentional disabling of the Watchdog, a special turn-off sequence must be fol- lowed when the Watchdog is disabled ...

  • Page 42

    ... WDTCR ori r16, (1<<WDCE)|(1<<WDE) out WDTCR, r16 ; Turn off WDT ldi r16, (0<<WDE) out WDTCR, r16 ret /* reset WDT */ _WDR(); /* Write logical one to WDCE and WDE */ WDTCR |= (1<<WDCE) | (1<<WDE); /* Turn off WDT */ WDTCR = 0x00; ATmega8A 42 ...

  • Page 43

    ... Initial Value • Bits 7:5 – Res: Reserved Bits These bits are reserved bits in the ATmega8A and will always read as zero. • Bit 4 – WDCE: Watchdog Change Enable This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog will not be disabled ...

  • Page 44

    ... WDP1 WDP0 Oscillator Cycles 0 0 16K (16,384 32K (32,768 64K (65,536 128K (131,072 256K (262,144 512K (524,288 1,024K (1,048,576 2,048K (2,097,152) ATmega8A Typical Time-out Typical Time-out 3. 5. 17.1 ms 16.3 ms 34.3 ms 32 0.14 s 0.13 s 0.27 s 0.26 s 0.55 s 0.52 s 1.1 s 1.0 s 2 ...

  • Page 45

    ... Interrupts This section describes the specifics of the interrupt handling performed by the ATmega8A. For a general explanation of the AVR interrupt handling, refer to page 13. 11.1 Interrupt Vectors in ATmega8A Table 11-1. Vector No Notes: Table 11-2 BOOTRST and IVSEL settings. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations ...

  • Page 46

    ... Table 11-2. BOOTRST Note: The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega8A is: addressLabels Code $000 $001 $002 $003 $004 $005 $006 $007 $008 $009 $00a $00b $00c $00d $00e $00f $010 $011 $012 ; $013 ...

  • Page 47

    ... SPM_RDY ; Store Program Memory Ready Handler rjmp RESET ; Reset handler RESET:ldi r16,high(RAMEND); Main program start out SPH,r16 ; Set Stack Pointer to top of RAM ldi r16,low(RAMEND) out SPL,r16 sei ; Enable interrupts <instr> xxx ATmega8A Comments ; Reset handler ; Set Stack Pointer to top of RAM 47 ...

  • Page 48

    ... SPL,r16 sei ; Enable interrupts <instr> xxx INT1 INT0 – – R/W R for details. To avoid unintentional changes of Interrupt Vector ATmega8A – – IVSEL IVCE R R R/W R “Boot Loader Support – Read-While-Write “Boot Loader for details on Boot Lock Bits. GICR 48 ...

  • Page 49

    ... Enable change of Interrupt Vectors ldi r16, (1<<IVCE) out GICR, r16 ; Move interrupts to boot Flash section ldi r16, (1<<IVSEL) out GICR, r16 ret /* Enable change of Interrupt Vectors */ GICR = (1<<IVCE); /* Move interrupts to boot Flash section */ GICR = (1<<IVSEL); ATmega8A 49 ...

  • Page 50

    ... Ground as indicated in CC for a complete list of parameters. Pxn C pin “Register Description” on page 55. Refer to the individual module sections for a full description of the alter- ATmega8A Figure 12-1. Refer to “Electrical Char Logic See Figure "General Digital I/O" for Details 65. “ ...

  • Page 51

    ... I/O CLOCK I/O 1. WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk and PUD are common to all ports. 65, the DDxn bits are accessed at the DDRx I/O address, the PORTxn bits ATmega8A Figure 12 DDxn Q CLR ...

  • Page 52

    ... Input 1 1 Input 0 X Output 1 X Output Figure 12-2, the PINxn Register bit and the preceding latch con- pd,max ATmega8A Pull-up Comment No Tri-state (Hi-Z) Pxn will source current if external pulled Yes low. No Tri-state (Hi-Z) No Output Low (Sink) No Output High (Source) Figure 12-3 ...

  • Page 53

    ... The out instruction sets the “SYNC LATCH” signal at the positive edge of through the synchronizer is 1 system clock period. pd SYSTEM CLK r16 out PORTx, r16 SYNC LATCH PINxn r17 ATmega8A XXX in r17, PINx 0x00 t pd, max t pd, min , a single signal transition on the pin will be delayed ...

  • Page 54

    ... Figure 12-2, the digital input signal can be clamped to ground at the input of the ATmega8A /2. CC “Alternate Port Functions” on page 55 ...

  • Page 55

    ... The overriding signals may not be present in all port pins, but the figure serves as a generic description applicable to all port pins in the AVR microcontroller family. 8159D–AVR–02/11 or GND is not recommended, since this may cause excessive currents if the pin is CC ATmega8A Figure 12-5 Figure 12-2 can be overridden by 55 ...

  • Page 56

    ... PUD are common to all ports. All other signals are unique for each pin. summarizes the function of the overriding signals. The pin and port indexes from are not shown in the succeeding tables. The overriding signals are generated internally ATmega8A PUOExn PUOVxn ...

  • Page 57

    ... Analog Input/output This is the Analog Input/output to/from alternate functions. The signal is connected directly to the pad, and can be used bi-directionally for more details about this feature. ATmega8A ACME PUD PSR2 PSR10 R/W R/W R/W R SFIOR “Con- ...

  • Page 58

    ... MISO (SPI Bus Master Input/Slave Output) MOSI (SPI Bus Master Output/Slave Input) OC2 (Timer/Counter2 Output Compare Match Output) SS (SPI Bus Master Slave select) OC1B (Timer/Counter1 Output Compare Match B Output) OC1A (Timer/Counter1 Output Compare Match A Output) ICP1 (Timer/Counter1 Input Capture Pin) ATmega8A Table 12- ...

  • Page 59

    ... MISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT. 8159D–AVR–02/11 and Table 12-4 relate the alternate functions of Port B to the overriding signals Figure 12-5 on page 56. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the ATmega8A 59 ...

  • Page 60

    ... PORTB3 • PUD SPE • MSTR 0 SPE • MSTR + OC2 ENABLE SPI MSTR OUTPUT + OC2 0 0 SPI SLAVE INPUT – ATmega8A PB5/SCK PB4/MISO SPE • MSTR SPE • MSTR PORTB5 • PUD PORTB4 • PUD SPE • MSTR SPE • MSTR 0 0 SPE • ...

  • Page 61

    ... SCL (Two-wire Serial Bus Clock Line) ADC4 (ADC Input Channel 4) PC4 SDA (Two-wire Serial Bus Data Input/Output Line) PC3 ADC3 (ADC Input Channel 3) PC2 ADC2 (ADC Input Channel 2) PC1 ADC1 (ADC Input Channel 1) PC0 ADC0 (ADC Input Channel 0) ATmega8A Table 12-5. 61 ...

  • Page 62

    ... When enabled, the Two-wire Serial Interface enables slew-rate controls on the output pins PC4 and PC5. This is not shown in the figure. In addition, spike filters are connected between the AIO outputs shown in the port figure and the digital logic of the TWI module. ATmega8A PC4/SDA/ADC4 TWEN PORTC4 • ...

  • Page 63

    ... AIN0 (Analog Comparator Positive Input) PD5 T1 (Timer/Counter 1 External Counter Input) XCK (USART External Clock Input/Output) PD4 T0 (Timer/Counter 0 External Counter Input) PD3 INT1 (External Interrupt 1 Input) PD2 INT0 (External Interrupt 0 Input) PD1 TXD (USART Output Pin) PD0 RXD (USART Input Pin) ATmega8A Table 12-8. 63 ...

  • Page 64

    ... AIN1 INPUT AIN0 INPUT PD3/INT1 PD2/INT0 INT1 ENABLE INT0 ENABLE 1 1 INT1 INPUT INT0 INPUT – – ATmega8A PD5/T1 PD4/XCK/ UMSEL 0 XCK OUTPUT INPUT XCK INPUT / T0 INPUT – – PD1/TXD PD0/RXD TXEN RXEN 0 PORTD0 • PUD TXEN RXEN 1 0 TXEN ...

  • Page 65

    ... PINC6 PINC5 PINC4 N/A N/A N PORTD7 PORTD6 PORTD5 PORTD4 R/W R/W R/W R DDD7 DDD6 DDD5 DDD4 R/W R/W R/W R ATmega8A PORTB3 PORTB2 PORTB1 PORTB0 R/W R/W R/W R DDB3 DDB2 DDB1 DDB0 R/W R/W R/W R PINB3 PINB2 PINB1 PINB0 N/A ...

  • Page 66

    ... PIND – The Port D Input Pins Address Bit Read/Write Initial Value 8159D–AVR–02/ PIND7 PIND6 PIND5 PIND4 N/A N/A N/A N/A ATmega8A PIND3 PIND2 PIND1 PIND0 N/A N/A N/A N/A PIND 66 ...

  • Page 67

    ... If the level is sampled twice by the Watchdog Oscillator clock but SM2 SM1 SM0 R/W R/W R/W R Table 13-1. The value on the INT1 pin is sampled before ATmega8A 244. The MCU will “System Clock and ISC11 ISC10 ISC01 ISC00 R/W R/W R/W R “Clock ...

  • Page 68

    ... The low level of INT0 generates an interrupt request. 1 Any logical change on INT0 generates an interrupt request. 0 The falling edge of INT0 generates an interrupt request. 1 The rising edge of INT0 generates an interrupt request INT1 INT0 – – R/W R ATmega8A – – IVSEL IVCE R R R/W R GICR 68 ...

  • Page 69

    ... Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared when INT0 is configured as a level interrupt. 8159D–AVR–02/ INTF1 INTF0 – – R/W R ATmega8A – – – – GIFR 69 ...

  • Page 70

    ... Timer/Counter number, in this case 0. However, when using the register or bit 8159D–AVR–02/11 “Pin Configurations” on page 2. CPU accessible I/O Registers, including I/O bits 73. TCCRn count Control Logic clk Timer/Counter TCNTn = 0xFF ATmega8A Figure 14-1. For the actual placement of TOVn (Int.Req.) Clock Select Tn Edge Tn Detector ( From Prescaler ) T0 ). ...

  • Page 71

    ... DATA BUS count TCNTn Control Logic Increment TCNT0 by 1. Timer/Counter clock, referred to as clk Tn Signalize that TCNT0 has reached maximum value. is present or not. A CPU write overrides (has priority over) all T0 ATmega8A 75. Figure 14-2 TOVn (Int. Req.) Clock Select Edge Detector clk Tn ...

  • Page 72

    ... Figure 14-3 contains timing data for basic Timer/Counter operation. The figure I/O Tn /1) I/O MAX - 1 shows the same timing data, but with the prescaler enabled. I/O Tn /8) I/O MAX - 1 ATmega8A ) is therefore shown MAX BOTTOM /8) clk_I/O MAX BOTTOM BOTTOM + 1 BOTTOM + 1 72 ...

  • Page 73

    ... External clock source on T0 pin. Clock on falling edge External clock source on T0 pin. Clock on rising edge TCNT0[7:0] R/W R/W R/W R OCIE2 TOIE2 TICIE1 OCIE1A R/W R/W R/W R ATmega8A – CS02 CS01 CS00 R R/W R/W R R/W R/W R/W R OCIE1B TOIE1 – ...

  • Page 74

    ... When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow interrupt is executed. 8159D–AVR–02/ OCF2 TOV2 ICF1 OCF1A R/W R/W R/W R ATmega8A OCF1B TOV1 – TOV0 R/W R/W R/W R TIFR 74 ...

  • Page 75

    ... Alternatively, one of four taps from the prescaler can be used as a CLK_I/O ). The T1/T0 pin is sampled once every system clock cycle by the pin synchronization T0 /clk T1 ATmega8A /8, f /64, f CLK_I/O CLK_I/O pulse for each positive (CSn2 negative T 0 ...

  • Page 76

    ... I/O Synchronization < f /2) given a 50/50% duty cycle. Since the edge detector uses ExtClk clk_I/O I/O Clear Synchronization Synchronization clk 1. The synchronization logic on the input pins ( ATmega8A D Q Edge Detector (1) T1 T1/T0) is shown in Figure Tn_sync (To Clock Select Logic) /2.5. clk_I/O clk T0 15-1. ...

  • Page 77

    ... Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both timers. This bit will always be read as zero. 8159D–AVR–02/ – – – – ATmega8A ACME PUD PSR2 PSR10 R/W R/W R/W R SFIOR 77 ...

  • Page 78

    ... I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit loca- tions are listed in the 8159D–AVR–02/11 “Pin Configurations” on page “Register Description” on page 99. ATmega8A Figure 16-1. For the actual 2. CPU accessible I/O Registers, 78 ...

  • Page 79

    ... PWM or variable frequency output on the Output Compare Pin (OC1A/B). 8159D–AVR–02/11 Count Clear Control Logic Direction Timer/Counter TCNTn = OCRnA = OCRnB ICRn TCCRnA 1. Refer to “Pin Configurations” on page Timer/Counter1 pin placement and description. ATmega8A (1) TOVn (Int. Req.) Clock Select clk Tn Edge Detector TOP BOTTOM ( From Prescaler ) = = 0 OCFnA (Int. Req.) ...

  • Page 80

    ... The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be one of the fixed values: 0x00FF, 0x01FF, or 0x03FF the value stored in the OCR1A or ICR1 Reg- ister. The assignment is dependent of the mode of operation. ATmega8A (see 80 ...

  • Page 81

    ... Therefore, when both 8159D–AVR–02/11 ( Set TCNT1 to 0x01FF ldi r17,0x01 ldi r16,0xFF out TCNT1H,r17 out TCNT1L,r16 ; Read TCNT1 into r17:r16 in r16,TCNT1L in r17,TCNT1H :. (1) unsigned int Set TCNT1 to 0x01FF */ TCNT1 = 0x1FF; /* Read TCNT1 into TCNT1 See “About Code Examples” on page 6. ATmega8A 81 ...

  • Page 82

    ... Restore Global Interrupt Flag out SREG,r18 ret (1) unsigned char sreg; unsigned int i; /* Save Global Interrupt Flag */ sreg = SREG; /* Disable interrupts */ _CLI(); /* Read TCNT1 into TCNT1; /* Restore Global Interrupt Flag */ SREG = sreg; return i; 1. See “About Code Examples” on page 6. ATmega8A 82 ...

  • Page 83

    ... TCNT1H,r17 out TCNT1L,r16 ; Restore Global Interrupt Flag out SREG,r18 ret (1) unsigned char sreg; unsigned int i; /* Save Global Interrupt Flag */ sreg = SREG; /* Disable interrupts */ _CLI(); /* Set TCNT1 TCNT1 = i; /* Restore Global Interrupt Flag */ SREG = sreg; 1. See “About Code Examples” on page 6. ATmega8A 75. 83 ...

  • Page 84

    ... Signalize that TCNT1 has reached minimum value (zero). ). The clk can be generated from an external or internal clock source present or not. A CPU write overrides (has priority over) all counter clear ATmega8A TOVn (Int. Req.) Clock Select Edge Detector clk Tn Control Logic ( From Prescaler ) ...

  • Page 85

    ... TEMP (8-bit) ICRnH (8-bit) ICRnL (8-bit) ICRn (16-bit Register) WRITE ACO* ACIC* Analog Comparator ICPn Figure 16-3. The elements of DATA BUS (8-bit) TCNTnH (8-bit) TCNTnL (8-bit) TCNTn (16-bit Counter) ICNC ICES Noise Edge Canceler Detector ATmega8A ICFn (Int. Req.) 85 ...

  • Page 86

    ... Measurement of an external signal’s duty cycle requires that the trigger edge is changed after each capture. Changing the edge sensing must be done as early as possible after the ICR1 8159D–AVR–02/11 81. ATmega8A “Accessing 16-bit Registers” (Figure 15-1 on page 76). The edge detector is also ...

  • Page 87

    ... DATA BUS TEMP (8-bit) OCRnxH Buf. (8-bit) OCRnxL Buf. (8-bit) OCRnx Buffer (16-bit Register) OCRnxH (8-bit) OCRnxL (8-bit) OCRnx (16-bit Register) TOP Waveform Generator BOTTOM ATmega8A 90.) (8-bit) TCNTnH (8-bit) TCNTnL (8-bit) TCNTn (16-bit Counter) = (16-bit Comparator ) OCFnx (Int.Req.) OCnx WGMn3:0 COMnx1:0 ...

  • Page 88

    ... Normal mode. The OC1x Register keeps its value even when changing between Waveform Generation modes. Be aware that the COM1x1:0 bits are not double buffered together with the compare value. Changing the COM1x1:0 bits will take effect immediately. 8159D–AVR–02/11 81. ATmega8A “Accessing 16-bit Registers” 88 ...

  • Page 89

    ... The waveform generator uses the COM1x1:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the COM1x1 tells the waveform generator that no action on the 8159D–AVR–02/11 COMnx1 Waveform COMnx0 Generator FOCnx clk I/O ATmega8A Figure 16-5 shows a simplified OCnx Pin OCnx 0 ...

  • Page 90

    ... Compare Match occurs with either OCR1A or ICR1, and then counter (TCNT1) is cleared. 8159D–AVR–02/11 Table 16-2 on page See “Compare Match Output Unit” on page 89. “Timer/Counter Timing Diagrams” on page ATmega8A 99. For fast PWM mode refer to Table 16-3 on Table 16-4 on 97. Figure 16-6 ...

  • Page 91

    ... PWM mode well suited for power regulation, rectification, and DAC 8159D–AVR–02/ when OCR1A is set to zero (0x0000). The waveform frequency clk_I -------------------------------------------------- - OCnA ⋅ ATmega8A OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) (COMnA1 clk_I/O ⋅ OCRnA ...

  • Page 92

    ... Compare Match at the TOP value. The counter will then have to count to 8159D–AVR–02/11 ( TOP log R = ---------------------------------- - FPWM log ATmega8A ) + Figure 16-7. The figure OCRnx / TOP Update and TOVn Interrupt Flag Set and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) (COMnx1 (COMnx1 ...

  • Page 93

    ... The PWM resolution for the phase correct PWM mode can be fixed to 8-, 9-, or 10-bit, or defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 8159D–AVR–02/11 Table 16-3 on page f clk_I ---------------------------------- - OCnxPWM ⋅ TOP when OCR1A is set to zero (0x0000). This feature clk_I/O 1 ATmega8A 100. The actual OC1x ) 93 ...

  • Page 94

    ... TOP value. When these two values differ the 8159D–AVR–02/ TOP log + ---------------------------------- - PCPWM log Figure 16-8 ATmega8A Figure 16-8. The figure OCRnx / TOP Update and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) TOVn Interrupt Flag Set (Interrupt on Bottom) (COMnx1 (COMnx1 illustrates, changing the 94 ...

  • Page 95

    ... In phase and frequency correct PWM mode the counter is incremented until the counter value matches either the value in ICR1 (WGM13:0 = 8), or the value in OCR1A (WGM13:0 = 9). The 8159D–AVR–02/11 f OCnxPCPWM 16-9 PFCPWM ATmega8A Table 16-4 on page f clk_I/O = --------------------------- - ⋅ ⋅ TOP ( ...

  • Page 96

    ... Figure 16-9. The figure shows phase and frequency correct shows the output generated is, in contrast to the Phase Correct mode, symmetri- ATmega8A OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) OCRnx / TOP Update and TOVn Interrupt Flag Set (Interrupt on Bottom) ...

  • Page 97

    ... OCRnx OCFnx Figure 16-11 8159D–AVR–02/11 f OCnxPFCPWM Figure 16-10 I/O Tn /1) I/O OCRnx - 1 shows the same timing data, but with the prescaler enabled. ATmega8A f clk_I/O = --------------------------- - ⋅ ⋅ TOP ) is therefore shown shows a timing diagram for the setting of OCF1x. OCRnx OCRnx + 1 OCRnx Value ...

  • Page 98

    ... Tn (clk /1) I/O TCNTn TOP - 1 TCNTn TOP - 1 (FPWM) (if used as TOP) OCRnx Old OCRnx Value shows the same timing data, but with the prescaler enabled. ATmega8A OCRnx OCRnx + 1 OCRnx Value TOP BOTTOM TOP TOP - 1 New OCRnx Value /8) clk_I/O OCRnx + 2 BOTTOM + 1 TOP - 2 98 ...

  • Page 99

    ... Compare Output Mode, Non-PWM COM1A0/ COM1B0 Description 0 Normal port operation, OC1A/OC1B disconnected. 1 Toggle OC1A/OC1B on Compare Match 0 Clear OC1A/OC1B on Compare Match (Set output to low level) 1 Set OC1A/OC1B on Compare Match (Set output to high level) ATmega8A /8) clk_I/O TOP BOTTOM TOP TOP - 1 New OCRnx Value ...

  • Page 100

    ... OC1A/OC1B on Compare Match when downcounting. 1 Set OC1A/OC1B on Compare Match when up-counting. Clear OC1A/OC1B on Compare Match when downcounting special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. “Phase Correct PWM Mode” on page 93. ATmega8A (1) for more details. See “Fast See 100 ...

  • Page 101

    ... CTC 0 1 (Reserved Fast PWM 1 1 Fast PWM ICNC1 ICES1 – R/W R ATmega8A (See “Modes of Operation” on page Update of TOP OCR1 0xFFFF Immediate 0x00FF TOP 0x01FF TOP 0x03FF TOP OCR1A Immediate 0x00FF BOTTOM 0x01FF BOTTOM 0x03FF BOTTOM ICR1 BOTTOM OCR1A ...

  • Page 102

    ... I clk /256 (From prescaler) I clk /1024 (From prescaler) I External clock source on T1 pin. Clock on falling edge External clock source on T1 pin. Clock on rising edge TCNT1[15:8] R/W R/W R/W R ATmega8A TCNT1[7:0] R/W R/W R Figure 0 TCNT1H TCNT1L R/W 0 102 ...

  • Page 103

    ... High byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. 8159D–AVR–02/ R/W R/W R/W R R/W R/W R/W R See “Accessing 16-bit Registers” on page 81 R/W R/W R/W R See “Accessing 16-bit Registers” on page 81. ATmega8A See “Accessing 16-bit OCR1A[15:8] OCR1A[7:0] R/W R/W R OCR1B[15:8] OCR1B[7:0] R/W R/W R ICR1[15:8] ICR1[7:0] R/W ...

  • Page 104

    ... TOV1 Flag, located in TIFR, is set OCF2 TOV2 ICF1 R/W R/W R This register contains flag bits for several Timer/Counters, but only Timer1 bits are described in this section. The remaining bits are described in their respective timer sections. ATmega8A OCIE1A OCIE1B TOIE1 – R/W R/W R ...

  • Page 105

    ... TOV1 Flag is set when the timer overflows. Refer to behavior when using another WGM13:0 bit setting. TOV1 is automatically cleared when the Timer/Counter1 Overflow Interrupt Vector is executed. Alternatively, TOV1 can be cleared by writing a logic one to its bit location. 8159D–AVR–02/11 ATmega8A Table 16-5 on page 101 for the TOV1 Flag 105 ...

  • Page 106

    ... I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the “Register Description” on page 8159D–AVR–02/11 “Pin Configurations” on page 2. CPU accessible I/O Registers, including I/O bits 121. ATmega8A Figure 17-1. For the actual placement of 106 ...

  • Page 107

    ... Control Logic direction BOTTOM TOP Timer/Counter TCNTn = 0 = 0xFF = OCRn Synchronized Status Flags Status Flags ASSRn asynchronous Mode Select (ASn ATmega8A TOVn (Int. Req.) clk Tn T/C Oscillator Prescaler clk OCn I/O (Int. Req.) Waveform OCn Generation clk I/O Synchronization Unit clk ASY see “ ...

  • Page 108

    ... DATA BUS count clear TCNTn Control Logic direction BOTTOM TOP Increment or decrement TCNT2 by 1. Selects between increment and decrement. Clear TCNT2 (set all bits to zero). ATmega8A I/O 118. For details on clock sources and 75. TOVn (Int. Req.) T/C clk Tn Oscillator Prescaler . When the AS2 “ ...

  • Page 109

    ... Signalizes that TCNT2 has reached minimum value (zero). ). clk can be generated from an external or internal clock source present or not. A CPU write overrides (has priority over) all counter clear or T2 112. 112). shows a block diagram of the Output Compare unit. ATmega8A (see “Modes of 109 ...

  • Page 110

    ... This feature allows OCR2 to be initialized to the same value as TCNT2 without triggering an interrupt when the Timer/Counter clock is enabled. 8159D–AVR–02/11 DATA BUS OCRn = (8-bit Comparator ) TOP BOTTOM Waveform Generator FOCn WGMn1:0 ATmega8A TCNTn OCFn (Int. Req.) OCxy COMn1:0 110 ...

  • Page 111

    ... PORT) that are affected by the COM21:0 bits are shown. When referring to the OC2 state, the reference is for the internal OC2 Register, not the OC2 pin. Figure 17-4. Compare Match Output Unit, Schematic 8159D–AVR–02/11 COMn1 Waveform COMn0 Generator FOCn clk I/O ATmega8A Figure 17-4 shows a simplified sche OCn OCn Pin 0 D ...

  • Page 112

    ... OCR2. The OCR2 defines the top value for the counter, hence also its 8159D–AVR–02/11 See “Register Description” on page 121. Table 17-3 on page 122. For fast PWM mode, refer to Table 17-5 on page “Timer/Counter Timing Diagrams” on page ATmega8A Table 17-4 on page 122. 111). 116. 112 ...

  • Page 113

    ... Match between TCNT2 and OCR2, and set at BOTTOM. In inverting Compare Output mode, the output is set on Compare Match and cleared at BOTTOM. Due to the single-slope operation, the 8159D–AVR–02/11 Figure clk_I ---------------------------------------------- - OCn ⋅ ⋅ OCRn 1 + ATmega8A 17-5. The counter value (TCNT2) OCn Interrupt Flag Set (COMn1 OC2 clk_I/O ) 113 /2 ...

  • Page 114

    ... PWM mode. If the OCR2 is set equal to BOTTOM, the output will be 8159D–AVR–02/11 Figure 17-6. The TCNT2 value is in the timing diagram shown as a his Table 17-4 on page f = OCnPWM ATmega8A OCRn Interrupt Flag Set OCRn Update and TOVn Interrupt Flag Set (COMn1 (COMn1 122). The actual OC2 value f ...

  • Page 115

    ... TCNT2 slopes represent compare matches between OCR2 and TCNT2. Figure 17-7. Phase Correct PWM Mode, Timing Diagram TCNTn OCn OCn Period 8159D–AVR–02/ when OCR2 is set to zero. This fea- oc2 clk_I ATmega8A Figure 17-7. OCn Interrupt Flag Set OCRn Update TOVn Interrupt Flag Set (COMn1 (COMn1 115 ...

  • Page 116

    ... OCnPCPWM Figure 17-7 OCn has a transition from high to low even though Figure contains timing data for basic Timer/Counter operation. The figure shows the ATmega8A Table 17-5 on page 122). The actual f clk_I/O ----------------- - ⋅ N 510 17-7. When the OCR2A value is MAX the ...

  • Page 117

    ... MAX - 1 shows the same timing data, but with the prescaler enabled. I/O Tn /8) I/O MAX - 1 shows the setting of OCF2 in all modes except CTC mode. I/O Tn /8) I/O OCRn - 1 ATmega8A MAX BOTTOM /8) clk_I/O MAX BOTTOM OCRn OCRn + 1 OCRn Value BOTTOM + 1 BOTTOM + 1 /8) ...

  • Page 118

    ... Otherwise, the MCU will enter sleep mode before the changes are effective. This is particularly important if the Output Compare2 interrupt is used to wake up the device, since 8159D–AVR–02/11 shows the setting of OCF2 and the clearing of TCNT2 in CTC mode. caler (f /8) clk_I/O I/O Tn /8) I/O TOP - 1 ATmega8A TOP BOTTOM TOP BOTTOM + 1 118 ...

  • Page 119

    ... Interrupt Flag. The Output Compare Pin is changed on the timer clock and is not synchronized to the processor clock. 8159D–AVR–02/11 ) again becomes active, TCNT2 will read as the previous value (before entering I/O ATmega8A 119 ...

  • Page 120

    ... AS2 PSR2 CS20 CS21 CS22 TIMER/COUNTER2 CLOCK SOURCE . By setting the AS2 bit in ASSR, Timer/Counter2 is asynchronously I/O /256, and clk /1024. Additionally, clk T2S T2S ATmega8A 10-BIT T/C PRESCALER 0 clk T2 . clk is by default connected to the main T2S T2S /8, clk /32, clk T2S T2S as well as 0 (stop) may be selected ...

  • Page 121

    ... The CTC2 and PWM2 bit definition names are now obsolete. Use the WGM21:0 definitions. However, the functionality and location of these bits are compatible with previous versions of the timer. Table 17-3 shows the COM21:0 bit functionality when the WGM21:0 bits are set to a ATmega8A ...

  • Page 122

    ... A special case occurs when OCR2 equals TOP and COM21 is set. In this case, the Compare Match is ignored, but the set or clear is done at TOP. See 115 for more details. ATmega8A (1) “Fast PWM Mode” on page 113 (1) “Phase Correct PWM Mode” on page ...

  • Page 123

    ... T2S 1 0 clk /256 (From prescaler clk /1024 (From prescaler TCNT2[7:0] R/W R/W R/W R OCR2[7:0] R/W R/W R/W R – – – – ATmega8A R/W R/W R/W R R/W R/W R/W R AS2 TCN2UB OCR2UB TCR2UB R When AS2 is I/O TCNT2 OCR2 ASSR 123 ...

  • Page 124

    ... Handling Vector. Alternatively, OCF2 is cleared by writing a logic one to 8159D–AVR–02/ OCIE2 TOIE2 TICIE1 OCIE1A R/W R/W R/W R OCF2 TOV2 ICF1 OCF1A R/W R/W R/W R ATmega8A OCIE1B TOIE1 – TOIE0 R/W R OCF1B TOV1 – TOV0 R/W R TIMSK ...

  • Page 125

    ... Timer/Counter2 is clocked by the internal CPU clock. If this bit is written when Timer/Counter2 is operating in Asynchronous mode, the bit will remain one until the prescaler has been reset. 8159D–AVR–02/ – – – – ATmega8A ACME PUD PSR2 PSR10 R/W R/W R/W R SFIOR 125 ...

  • Page 126

    ... Wake-up from Idle Mode • Double Speed (CK/2) Master SPI Mode 18.2 Overview The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega8A and peripheral devices or between several AVR devices. Figure 18-1. SPI Block Diagram Note: 8159D–AVR–02/11 (1) DIVIDER /2/4/8/16/32/64/128 1 ...

  • Page 127

    ... Low period: longer than 2 CPU clock cycles High period: longer than 2 CPU clock cycles. 8159D–AVR–02/11 MSB MASTER LSB 8 BIT SHIFT REGISTER SPI CLOCK GENERATOR V ATmega8A Figure MSB SLAVE MISO MISO 8 BIT SHIFT REGISTER MOSI MOSI SCK SCK ...

  • Page 128

    ... Direction, Master SPI User Defined Input User Defined User Defined 1. See “Port B Pins Alternate Functions” on page 58 the direction of the user defined SPI pins. ATmega8A “Alternate Port Direction, Slave SPI Input User Defined Input Input for a detailed description of how to define 128 ...

  • Page 129

    ... Set MOSI and SCK output, all others input */ DDR_SPI = (1<<DD_MOSI)|(1<<DD_SCK); /* Enable SPI, Master, set clock rate fck/16 */ SPCR = (1<<SPE)|(1<<MSTR)|(1<<SPR0); /* Start transmission */ SPDR = cData; /* Wait for transmission complete */ while(!(SPSR & (1<<SPIF))) ; 1. See “About Code Examples” on page 6. ATmega8A 129 ...

  • Page 130

    ... Read received data and return in r16,SPDR ret (1) /* Set MISO output, all others input */ DDR_SPI = (1<<DD_MISO); /* Enable SPI */ SPCR = (1<<SPE); /* Wait for reception complete */ while(!(SPSR & (1<<SPIF))) ; /* Return data register */ return SPDR; 1. See “About Code Examples” on page 6. ATmega8A 130 ...

  • Page 131

    ... Data bits are shifted out and latched in on opposite edges of the SCK sig- and Table 18-3, as done below: CPOL and CPHA Functionality Leading Edge Sample (Rising) Setup (Rising) Sample (Falling) Setup (Falling) ATmega8A Figure Trailing Edge SPI Mode Setup (Falling) 0 Sample (Falling) 1 Setup (Rising) 2 ...

  • Page 132

    ... SCK (CPOL = 0) mode 1 SCK (CPOL = 1) mode 3 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS MSB first (DORD = 0) MSB Bit 6 LSB first (DORD = 1) LSB Bit 1 ATmega8A Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 2 Bit 3 ...

  • Page 133

    ... R Figure 18-3 and Figure 18-4 CPOL Functionality CPOL Leading Edge 0 Rising 1 Falling Figure 18-3 CPHA Functionality CPHA Leading Edge 0 Sample 1 Setup ATmega8A MSTR CPOL CPHA SPR1 R/W R/W R/W R for an example. The CPOL functionality is sum- Trailing Edge Falling Rising and Figure 18-4 for an example ...

  • Page 134

    ... Master mode (see clock periods. When the SPI is configured as Slave, the SPI is only guaranteed to work lower. The SPI interface on the ATmega8A is also used for Program memory and EEPROM download- ing or uploading. See 8159D–AVR–02/11 Relationship Between SCK and the Oscillator Frequency ...

  • Page 135

    ... The SPI Data Register is a Read/Write Register used for data transfer between the Register File and the SPI Shift Register. Writing to the register initiates data transmission. Reading the regis- ter causes the Shift Register Receive buffer to be read. 8159D–AVR–02/ MSB R/W R/W R/W R ATmega8A LSB R/W R/W R/W R SPDR Undefined 135 ...

  • Page 136

    ... Overview The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART highly-flexible serial communication device. A simplified block diagram of the USART Transmit- ter is shown in 8159D–AVR–02/11 Figure 19-1. CPU accessible I/O Registers and I/O pins are shown in bold. ATmega8A 136 ...

  • Page 137

    ... UBRR[H:L] BAUD RATE GENERATOR UDR (Transmit) TRANSMIT SHIFT REGISTER RECEIVE SHIFT REGISTER UDR (Receive) UCSRA 1. Refer to “Pin Configurations” on page for USART pin placement. ATmega8A Clock Generator OSC SYNC LOGIC PIN CONTROL Transmitter TX CONTROL PARITY GENERATOR PIN CONTROL ...

  • Page 138

    ... When using Synchronous mode (UMSEL = 1), the Data Direction Register for the XCK pin (DDR_XCK) controls whether the clock source is internal (Master mode) or external (Slave mode). The XCK pin is only active when using Synchronous mode. Figure 19-2 8159D–AVR–02/11 shows a block diagram of the clock generation logic. ATmega8A Figure 19-1) if the Buffer Registers 138 ...

  • Page 139

    ... Clock output to XCK pin (Internal Signal). Used for synchronous master operation. XTAL pin frequency (System Clock). contains equations for calculating the baud rate (in bits per second) and for calculat- U2X / DDR_XCK Edge Detector UCPOL Figure 19-2. ATmega8A txclk 1 0 UMSEL 1 1 rxclk 0 139 ...

  • Page 140

    ... Baud rate (in bits per second, bps) System Oscillator clock frequency Contents of the UBRRH and UBRRL Registers 4095) 161). Figure 19-2 for details. depends on the stability of the system clock source therefore recommended to osc ATmega8A Equation for Calculating (1) Baud Rate UBRR Value f OSC UBRR ...

  • Page 141

    ... Bits inside brackets are FRAME (IDLE Start bit, always low. Data bits (0 to 8). Parity bit. Can be odd or even. Stop bit, always high. No transfers on the communication line (RxD or TxD). An IDLE line must be high. ATmega8A Sample Sample [5] [6] [7] [8] [P] Sp1 [Sp2] (St / IDLE) 141 ...

  • Page 142

    ... even n 1 – ⊕ odd n 1 – Parity bit using even parity. even Parity bit using odd parity. odd Data bit n of the character. n ATmega8A … ⊕ ⊕ ⊕ ⊕ ⊕ … ⊕ ⊕ ⊕ ⊕ ⊕ ...

  • Page 143

    ... Set baud rate */ UBRRH = (unsigned char)(ubrr>>8); UBRRL = (unsigned char)ubrr; /* Enable receiver and transmitter */ UCSRB = (1<<RXEN)|(1<<TXEN); /* Set frame format: 8data, 2stop bit */ UCSRC = (1<<URSEL)|(1<<USBS)|(3<<UCSZ0); 1. See “About Code Examples” on page 6. ATmega8A 143 ...

  • Page 144

    ... UCSRA,UDRE rjmp USART_Transmit ; Put data (r16) into buffer, sends the data out UDR,r16 ret (1) /* Wait for empty transmit buffer */ while ( !( UCSRA & (1<<UDRE Put data into buffer, sends the data */ UDR = data; 1. See “About Code Examples” on page 6. ATmega8A 144 ...

  • Page 145

    ... UCSRB |= (1<<TXB8); /* Put data into buffer, sends the data */ UDR = data; 1. These transmit functions are written to be general functions. They can be optimized if the con- tents of the UCSRB is static. I.e. only the TXB8 bit of the UCSRB Register is used after initialization. ATmega8A 145 ...

  • Page 146

    ... Shift Register will be moved into the receive buffer. The receive buffer can then be read by reading the UDR I/O location. The following code example shows a simple USART receive function based on polling of the Receive Complete (RXC) Flag. When using frames with less than eight bits the most significant 8159D–AVR–02/11 ATmega8A 146 ...

  • Page 147

    ... UCSRA, RXC rjmp USART_Receive ; Get and return received data from buffer in r16, UDR ret (1) /* Wait for data to be received */ while ( !(UCSRA & (1<<RXC Get and return received data from buffer */ return UDR; 1. See “About Code Examples” on page 6. ATmega8A 147 ...

  • Page 148

    ... UCSRA; resh = UCSRB; resl = UDR error, return - status & (1<<FE)|(1<<DOR)|(1<<PE) ) return -1; /* Filter the ninth bit, then return */ resh = (resh >> 1) & 0x01; return ((resh << resl); 1. See “About Code Examples” on page 6. ATmega8A 148 ...

  • Page 149

    ... The result of the check is stored in the receive buffer together with the received data and stop bits. The Parity Error (PE) Flag can then be read by software to check if the frame had a parity error. 8159D–AVR–02/11 and “Parity Checker” on page 149. ATmega8A 149 ...

  • Page 150

    ... RxD line is idle (i.e., no communication activity). 8159D–AVR–02/11 (1) sbis UCSRA, RXC ret in r16, UDR rjmp USART_Flush (1) unsigned char dummy; while ( UCSRA & (1<<RXC) ) dummy = UDR; 1. See “About Code Examples” on page 6. ATmega8A Figure 19-5 150 ...

  • Page 151

    ... Note that the Receiver only uses the first stop bit of a frame. Figure 19-7 of the next frame. 8159D–AVR–02/11 IDLE Figure 19 shows the sampling of the stop bit and the earliest possible beginning of the start bit ATmega8A START shows the sampling of the data bits and BIT ...

  • Page 152

    ... Receiver baud rate the ratio of the fastest incoming data rate that can be fast accepted in relation to the Receiver baud rate. and Table 19-3 list the maximum Receiver baud rate error that can be tolerated. Note ATmega8A STOP 1 (A) ( ...

  • Page 153

    ... ATmega8A Max Total Error Recommended Max Receiver (%) Error (%) +6.67/-6.8 ± 3.0 +5.79/-5.88 ± 2.0 +5.11/-5.19 ± 2.0 +4.58/-4.54 ± 2.0 +4.14/-4.19 ± 1.5 +3.78/-3.83 ± ...

  • Page 154

    ... When doing a write access of this I/O location, the high bit of the value written, the USART Reg- ister Select (URSEL) bit, controls which one of the two registers that will be written. If URSEL is zero during a write operation, the UBRRH value will be updated. If URSEL is one, the UCSRC setting will be updated. 8159D–AVR–02/11 ATmega8A 154 ...

  • Page 155

    ... UCSRC,r16 :. ( Set UBRRH UBRRH = 0x02 Set the USBS and the UCSZ1 bit to one, and */ /* the remaining bits to zero. */ UCSRC = (1<<URSEL)|(1<<USBS)|(1<<UCSZ1 See “About Code Examples” on page 6. ATmega8A 155 ...

  • Page 156

    ... SBIS), since these also will change the state of the FIFO. 8159D–AVR–02/11 (1) ; Read UCSRC in r16,UBRRH in r16,UCSRC ret (1) unsigned char ucsrc; /* Read UCSRC */ ucsrc = UBRRH; ucsrc = UCSRC; return ucsrc; 1. See “About Code Examples” on page R/W R/W R ATmega8A RXB[7:0] TXB[7:0] R/W R/W R/W R UDR (Read) UDR (Write) R/W 0 156 ...

  • Page 157

    ... This bit only has effect for the asynchronous operation. Write this bit to zero when using syn- chronous operation. Writing this bit to one will reduce the divisor of the baud rate divider from effectively dou- bling the transfer rate for asynchronous communication. 8159D–AVR–02/ RXC TXC UDRE ATmega8A DOR PE U2X MPCM R R R/W R UCSRA 157 ...

  • Page 158

    ... RXB8 is the ninth data bit of the received character when operating with serial frames with nine data bits. Must be read before reading the low bits from UDR. 8159D–AVR–02/11 “Multi-processor Communication Mode” on page RXCIE TXCIE UDRIE RXEN R/W R/W R/W R ATmega8A 153 TXEN UCSZ2 RXB8 TXB8 R/W R UCSRB 158 ...

  • Page 159

    ... UMSEL Bit Settings UMSEL Mode 0 Asynchronous Operation 1 Synchronous Operation UPM Bits Settings UPM1 UPM0 USBS Bit Settings USBS 0 1 ATmega8A UPM0 USBS UCSZ1 UCSZ0 R/W R/W R/W R section which describes how to access this register. Parity Mode Disabled Reserved Enabled, Even Parity ...

  • Page 160

    ... Falling XCK Edge URSEL – – R R/W R/W R/W R section which describes how to access this register. ATmega8A UCSZ0 Character Size 0 5-bit 1 6-bit 0 7-bit 1 8-bit 0 Reserved 1 Reserved 0 Reserved 1 9-bit Received Data Sampled (Input on RxD Pin) Falling XCK Edge Rising XCK Edge 12 11 ...

  • Page 161

    ... ATmega8A 19-9. UBRR values U2X = 1 UBRR Error 103 0.2% 51 0.2% 25 0.2% 16 2.1% 12 0.2% 8 -3.5% 6 -7.0% 3 8.5% 2 8.5% 1 8.5% – – 0 0.0% ...

  • Page 162

    ... Mbps 460.8 kbps ATmega8A U2X = 1 UBRR Error 383 0.0% 191 0.0% 95 0.0% 63 0.0% 47 0.0% 31 0.0% 23 0.0% 15 0.0% 11 0.0% 7 0.0% 3 0.0% 3 -7.8% 1 -7.8% 0 -7.8% 921 ...

  • Page 163

    ... ATmega8A U2X = 1 UBRR Error 767 0.0% 383 0.0% 191 0.0% 127 0.0% 95 0.0% 63 0.0% 47 0.0% 31 0.0% 23 0.0% 15 0.0% 7 0.0% 6 5.3% 3 -7.8% 1 -7.8% 1 ...

  • Page 164

    ... Mbps 1.25 Mbps ATmega8A U2X = 1 UBRR Error 1041 0.0% 520 0.0% 259 0.2% 173 -0.2% 129 0.2% 86 -0.2% 64 0.2% 42 0.9% 32 -1.4% 21 -1.4% 10 -1. ...

  • Page 165

    ... Bus Interface Unit START / STOP Spike Suppression Control Address/Data Shift Arbitration detection Register (TWDR) Address Match Unit Address Register (TWAR) Address Comparator ATmega8A Figure 20-1. All registers Spike Filter Bit Rate Generator Prescaler Bit Rate Register Ack (TWBR) Control Unit Status Register ...

  • Page 166

    ... MCU to wake up if addressed by a Master. If another interrupt (e.g., INT0) 8159D–AVR–02/11 SCL frequency Pull-up resistor values should be selected according to the SCL frequency and the capacitive bus line load. See Table 25-4 on page 248 ATmega8A CPU Clock frequency = ---------------------------------------------------------- - TWPS ⋅ ...

  • Page 167

    ... TWI bus lines. All devices connected to the bus have individual addresses, and mechanisms for resolving bus contention are inherent in the TWI protocol. Figure 20-2. TWI Bus Interconnection 8159D–AVR–02/11 Device 1 Device 2 Device 3 SDA SCL ATmega8A V CC ........ Device 167 ...

  • Page 168

    ... The device placing data on the bus. The device reading data from the bus. Figure 20-2, both bus lines are connected to the positive supply voltage through “Two-wire Serial Interface Characteristics” on page SDA SCL Data Stable Data Change ATmega8A 248. Two Data Stable 168 ...

  • Page 169

    ... Note that transmitting the general call address followed by a Read bit is meaningless, as this would cause contention if several slaves started transmitting different data. All addresses of the format 1111 xxx should be reserved for future purposes. 8159D–AVR–02/11 START STOP ATmega8A START REPEATED START STOP 169 ...

  • Page 170

    ... Addr MSB 1 START Data MSB SDA 1 2 SLA+R/W shows a typical data transmission. Note that several data bytes can be transmitted Addr LSB R Data LSB ACK Data Byte ATmega8A ACK 9 STOP, REPEATED START or Next Data Byte 170 ...

  • Page 171

    ... Master with the longest low period. Note that all masters listen to the SCL line, effectively starting to count their SCL high and low time-out periods when the combined SCL line goes high or low, respectively. 8159D–AVR–02/11 Addr LSB R/W ACK Data MSB ATmega8A Data LSB ACK Data Byte STOP 171 ...

  • Page 172

    ... Note that arbitration is not allowed between: 8159D–AVR–02/11 TA low Line TB Masters Start Counting Low Period START SDA from Master A SDA from Master B SDA Line SCL Line ATmega8A TA high TB low high Masters Start Counting High Period Master A Loses Arbitration, SDA A SDA 172 ...

  • Page 173

    ... TWCR, making sure that TWINT is written to one SLA TWINT set. Status code indicates SLA+W sent, ACK received ATmega8A 7. Check TWSR to see if data was sent and ACK received. Application loads appropriate control signals to send STOP into TWCR, making sure that TWINT is written to one Data A STOP 6 ...

  • Page 174

    ... Even though this example is simple, it shows the principles involved in all TWI transmissions. These can be summarized as follows: • When the TWI has finished an operation and expects application response, the TWINT Flag is set. The SCL line is pulled low until TWINT is cleared. 8159D–AVR–02/11 ATmega8A 174 ...

  • Page 175

    ... TWINT clears the flag. The TWI will then commence executing whatever operation was specified by the TWCR setting. In the following an assembly and C implementation of the example is given. Note that the code below assumes that several definitions have been made, for example by using include-files. 8159D–AVR–02/11 ATmega8A 175 ...

  • Page 176

    ... MT_DATA_ACK) ERROR(); TWCR = (1<<TWINT)|(1<<TWEN)| (1<<TWSTO); ATmega8A Comments Send START condition Wait for TWINT Flag set. This indicates that the START condition has been transmitted Check value of TWI Status Register. Mask prescaler bits. If ...

  • Page 177

    ... TWINT Flag is set. The num- Table 20-3 to Table 20-7. Note that the prescaler bits are masked to zero in 20-11). In order to enter a Master mode, a START condition must be transmitted. Device 1 Device 2 Device 3 MASTER SLAVE TRANSMITTER RECEIVER SDA SCL ATmega8A V CC ........ Device 177 ...

  • Page 178

    ... After a repeated START condition (state 0x10) the Two-wire Serial Interface can access the same Slave again new Slave without transmitting a STOP condi- tion. Repeated START enables the Master to switch between Slaves, Master Transmitter mode and Master Receiver mode without losing control of the bus: ATmega8A TWWC TWEN – ...

  • Page 179

    ... No TWDR action TWDR action TWDR action ATmega8A TWEA Next Action Taken by TWI Hardware X SLA+W will be transmitted; ACK or NOT ACK will be received X SLA+W will be transmitted; ACK or NOT ACK will be received X SLA+R will be transmitted; Logic will switch to Master Receiver mode X Data byte will be transmitted and ACK or NOT ACK will ...

  • Page 180

    ... W A $08 $18 A $20 Other master continues $38 Other master A continues $68 $78 DATA From master to slave From slave to master n 20-13). In order to enter a Master mode, a START condition must be transmitted. ATmega8A DATA A P $28 R SLA S $ $30 Other master continues $38 To corresponding $B0 states in slave mode Any number of data bytes ...

  • Page 181

    ... TWEA TWSTA TWINT TWEA TWSTA Table 20-4. Received data can be read from the TWDR Register when the TWINT TWINT TWEA TWSTA TWINT TWEA TWSTA ATmega8A V CC ........ Device TWSTO TWWC TWEN Table 20-3). In order to enter MR mode, TWSTO TWWC TWEN TWSTO TWWC TWEN 1 ...

  • Page 182

    ... Read data byte Read data byte Read data byte ATmega8A TWEA Next Action Taken by TWI Hardware X SLA+R will be transmitted ACK or NOT ACK will be received X SLA+R will be transmitted ACK or NOT ACK will be received X SLA+W will be transmitted Logic will switch to Master Transmitter mode ...

  • Page 183

    ... All the status codes mentioned in this section assume that the prescaler bits Data transfer in Slave Receiver mode Device 1 Device 2 Device 3 SLAVE MASTER RECEIVER TRANSMITTER SDA SCL TWA6 TWA5 TWA4 Device’s Own Slave Address ATmega8A A DATA A P $50 $58 R SLA S $10 Other master A continues $38 ...

  • Page 184

    ... Note that the Two-wire Serial Interface Data Register – TWDR does not reflect the last byte present on the bus when waking up from these Sleep modes. 8159D–AVR–02/11 TWINT TWEA TWSTA TWSTO ATmega8A TWWC TWEN – TWIE Table 20-6. 184 ...

  • Page 185

    ... ATmega8A TWEA Next Action Taken by TWI Hardware 0 Data byte will be received and NOT ACK will be returned 1 Data byte will be received and ACK will be returned 0 Data byte will be received and NOT ACK will be returned 1 Data byte will be received and ACK will be returned ...

  • Page 186

    ... General Call A $70 A $78 DATA From master to slave From slave to master n 20-16). All the status codes mentioned in this section assume that the prescaler bits Device 1 Device 2 Device 3 SLAVE MASTER TRANSMITTER RECEIVER SDA SCL ATmega8A DATA A DATA $80 $80 $ $88 DATA A DATA $90 $90 $A0 ...

  • Page 187

    ... Note that the Two-wire Serial Interface Data Register – TWDR does not reflect the last byte present on the bus when waking up from these sleep modes. 8159D–AVR–02/11 TWA6 TWA5 TWA4 TWA3 Device’s Own Slave Address TWINT TWEA TWSTA TWSTO ATmega8A TWA2 TWA1 TWA0 TWGCE TWWC TWEN – TWIE Table 20-7. 187 ...

  • Page 188

    ... SLA R A $A8 A $B0 DATA From master to slave From slave to master n ATmega8A TWEA Next Action Taken by TWI Hardware 0 Last data byte will be transmitted and NOT ACK should be received 1 Data byte will be transmitted and ACK should be re- ceived 0 Last data byte will be transmitted and NOT ACK should ...

  • Page 189

    ... STA STO TWINT No TWDR action No TWCR action No TWDR action ATmega8A Table TWEA Next Action Taken by TWI Hardware Wait or proceed current transfer X Only the internal hardware is affected, no STOP condi- tion is sent on the bus. In all cases, the bus is released and TWSTO is cleared. 20-9. ...

  • Page 190

    ... SLA+W A ADDRESS A Transmitted from master to slave Device 1 Device 3 Device 2 MASTER SLAVE MASTER TRANSMITTER TRANSMITTER RECEIVER SDA SCL Figure 20-19. Possible status values are given in circles. ATmega8A Master Receiver Rs SLA+R A DATA Rs = REPEATED START Transmitted from slave to master V CC ........ R1 R2 Device STOP 190 ...

  • Page 191

    ... TWSTA TWSTO R/W R/W R ATmega8A Data Arbitration lost in Data 38 TWI bus will be released and not addressed slave mode will be entered A START condition will be transmitted when the bus becomes free 68/78 Data byte will be received and NOT ACK will be returned Data byte will be received and ACK will be returned ...

  • Page 192

    ... This bit is a reserved bit and will always read as zero. • Bit 0 – TWIE: TWI Interrupt Enable When this bit is written to one, and the I-bit in SREG is set, the TWI interrupt request will be acti- vated for as long as the TWINT Flag is high. 8159D–AVR–02/11 ATmega8A 192 ...

  • Page 193

    ... TWS7 TWS6 TWS5 TWS4 TWPS0 “Bit Rate Generator Unit” on page TWD7 TWD6 TWD5 TWD4 R/W R/W R/W R ATmega8A TWS3 – TWPS1 TWPS0 R R R/W R Prescaler Value 166. The value of TWPS1:0 is used TWD3 TWD2 TWD1 TWD0 R/W R/W R/W R/W 1 ...

  • Page 194

    ... Bit 0 – TWGCE: TWI General Call Recognition Enable Bit If set, this bit enables the recognition of a General Call given over the Two-wire Serial Bus. 8159D–AVR–02/ TWA6 TWA5 TWA4 TWA3 R/W R/W R/W R ATmega8A TWA2 TWA1 TWA0 TWGCE R/W R/W R/W R TWAR 194 ...

  • Page 195

    ... Analog Comparator, as shown in 8159D–AVR–02/11 Figure 21-1. BANDGAP ACBG (1) OUTPUT 1. See Table 21-1 on page 196. 2. Refer to “Pin Configurations” on page 2 placement. (1) ATmega8A (2) and Table 12-8 on page 63 for Analog Comparator pin pins to replace the negative input to the Analog Com- Table 195 ...

  • Page 196

    ... ADC7:6 are only available in TQFP and QFN/MLF Package – – – “Analog Comparator Multiplexed Input” on page ACD ACBG ACO R/W R N/A ATmega8A (1) Analog Comparator Negative Input AIN1 AIN1 ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 ADC6 ADC7 – ACME PUD PSR2 R R/W R/W R/W 0 ...

  • Page 197

    ... Interrupt Enable bit in the ACSR Register. Otherwise an interrupt can occur when the bits are changed. 8159D–AVR–02/11 Table 21-2. ACIS1/ACIS0 Settings ACIS0 Interrupt Mode 0 Comparator Interrupt on Output Toggle 1 Reserved 0 Comparator Interrupt on Falling Output Edge 1 Comparator Interrupt on Rising Output Edge ATmega8A 197 ...

  • Page 198

    ... Sleep Mode Noise Canceler 22.2 Overview The ATmega8A features a 10-bit successive approximation ADC. The ADC is connected to an 8-channel Analog Multiplexer which allows eight single-ended voltage inputs constructed from the pins of Port C. The single-ended voltage inputs refer to 0V (GND). The ADC contains a Sample and Hold circuit which ensures that the input voltage to the ADC is held at a constant level during conversion ...

  • Page 199

    ... DATA BUS ADC MULTIPLEXER SELECT (ADMUX) MUX DECODER INTERNAL 2.56V REFERENCE BANDGAP REFERENCE INPUT MUX CC ATmega8A ADC CONVERSION COMPLETE IRQ 15 ADC DATA REGISTER ADC CTRL. & STATUS REGISTER (ADCSRA) (ADCH/ADCL) PRESCALER CONVERSION LOGIC SAMPLE & HOLD COMPARATOR ...

  • Page 200

    ... If a lower resolution than 10 bits is needed, the input clock frequency to the ADC can be higher than 200kHz to get a higher sample rate. 8159D–AVR–02/11 ADEN Reset START 7-BIT ADC PRESCALER CK ADPS0 ADPS1 ADPS2 ADC CLOCK SOURCE ATmega8A 200 ...