DSPIC33FJ12MC202-I/ML Microchip Technology, DSPIC33FJ12MC202-I/ML Datasheet - Page 28

• Manufacturer Part Number: DSPIC33FJ12MC202-I/ML
• Description: IC DSPIC MCU/DSP 12K 28QFN
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ12MC202-I/ML

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 12KB (12K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 6x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Core Frequency: 40MHz
• Core Supply Voltage: 2.75V
• Embedded Interface Type: I2C, JTAG, SPI, UART
• No. Of I/o's: 21
• Flash Memory Size: 12KB
• Supply Voltage Range: 3V To 3.6V
• Package: 28QFN EP
• Device Core: dsPIC
• Family Name: dSPIC33
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 21
• Interface Type: I2C/SPI/UART
• On-chip Adc: 6-chx10-bit|6-chx12-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164336 - MODULE SOCKET FOR PM3 28/44QFNDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

4.2.10
The ERASEP command instructs the programming
executive to page erase [NUM_PAGES] of code mem-
ory. The code memory must be erased at an “even” 512
instruction word address boundary
Expected Response (2 words):
0x1900
0x0002
DS70152H-page 28
Opcode
Length
NUM_PAGES Up to 255
Addr_MSB
Addr_LS
15
Opcode
Field
NUM_PAGES
ERASEP
12 11
0x9
0x3
Most Significant Byte of the 24-bit
address
Least Significant 16 bits of the 24-bit
address
COMMAND
Addr_LS
8 7
Description
Length
Addr_MSB
0
4.2.11
The CRCP command performs a CRC-16 on the range
of memory specified. This command can substitute for
a full chip verify. Data is shifted in a packed method as
demonstrated
Significant Byte first.
Example:
CRC-CITT-16 with test data of “123456789” becomes
0x29B1
Expected Response (3 words):
QE_Code: 0x1C00
Length: 0x0003
CRC Value: 0xXXXX
Opcode
Length
Reserved
Addr_MSB
Addr_LSW
Size
15
Opcode
Field
Reserved
Reserved
CRCP
12 11
0xC
0x5
0x0
Most Significant Byte of 24-bit
address
Least Significant 16 bits of 24-bit
address
Number of 24-bit locations (address
range divided by 2)
in
COMMAND
Addr_LSW
Size_LSW
Figure
© 2010 Microchip Technology Inc.
8 7
Description
4-4,
Length
byte-wise
Addr_MSB
Size_MSB
Least
0