DSPIC33FJ12MC202-I/ML Microchip Technology, DSPIC33FJ12MC202-I/ML Datasheet - Page 82

• Manufacturer Part Number: DSPIC33FJ12MC202-I/ML
• Description: IC DSPIC MCU/DSP 12K 28QFN
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ12MC202-I/ML

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 12KB (12K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 6x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Core Frequency: 40MHz
• Core Supply Voltage: 2.75V
• Embedded Interface Type: I2C, JTAG, SPI, UART
• No. Of I/o's: 21
• Flash Memory Size: 12KB
• Supply Voltage Range: 3V To 3.6V
• Package: 28QFN EP
• Device Core: dsPIC
• Family Name: dSPIC33
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 21
• Interface Type: I2C/SPI/UART
• On-chip Adc: 6-chx10-bit|6-chx12-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164336 - MODULE SOCKET FOR PM3 28/44QFNDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Revision H (October 2010)
This revision includes the following updates:
• Text and formatting updates have been
• All references to V
• All occurrences of PGC and PGD have been
• Added topics covered in
• Moved the Checksum Computation table to the
• Updated all occurrences of TBLPG to TBLPAG
• Removed the ERASEB command from the
• Updated the High-Level Enhanced ICSP™
• Replaced the Device Configuration Register Map
• Updated the Note in
• Changed Opcode 0x7 to Reserved in the
• Removed 4.2.10 “ERASEB Command”
• Updated the table cross-references in
• Combined all Default Configuration Register
• Relocated the paragraph on ICSP programming
• Added a Note to
• Updated Step 4 in Programming the Programming
• Updated Device IDs and Revision IDs (see
• Updated parameters D111, P1, P1A and P1B in
• Added Checksum Computation Example When
DS70152H-page 82
incorporated throughout the document
changed to: V
changed to PGCx and PGDx, respectively
Overview”
appendix (see
throughout the document
Command Set Summary (see
Programming Flow (see
(previously Table 4-3) with individual tables for
each dsPIC33F/PIC24H device family (see
Table 3-3
“Programming Methodology”
Programming Executive Command Set (see
Table
Section 5.7 “Writing Configuration Memory”
Values tables into one table (see
details, which now appears just before
Executive (see
Table
the AC/DC Characteristics and Timing
Requirements (see
Using CodeGuard™ Security (see
4-1)
7-1)
through
CAP
Table
Table
Section 6.1 “Overview”
Table
CAP
Table
Section 3.6.2
D-1)
6-1)
/V
DDCORE
3-12)
Figure
Section 1.0 “Device
8-1)
Table
3-1)
have been
Table
Table
3-1)
Table 5-7
5-6)
D-2).
© 2010 Microchip Technology Inc.