DSPIC33FJ12MC202-I/ML Microchip Technology, DSPIC33FJ12MC202-I/ML Datasheet - Page 35

• Manufacturer Part Number: DSPIC33FJ12MC202-I/ML
• Description: IC DSPIC MCU/DSP 12K 28QFN
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ12MC202-I/ML

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 12KB (12K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 6x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Core Frequency: 40MHz
• Core Supply Voltage: 2.75V
• Embedded Interface Type: I2C, JTAG, SPI, UART
• No. Of I/o's: 21
• Flash Memory Size: 12KB
• Supply Voltage Range: 3V To 3.6V
• Package: 28QFN EP
• Device Core: dsPIC
• Family Name: dSPIC33
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 21
• Interface Type: I2C/SPI/UART
• On-chip Adc: 6-chx10-bit|6-chx12-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164336 - MODULE SOCKET FOR PM3 28/44QFNDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

5.4
5.4.1
Flash memory write and erase operations are
controlled by the NVMCON register. Programming is
performed by setting NVMCON to select the type of
erase
(Table
the WR control bit (NVMCON<15>).
In ICSP mode, all programming operations are
self-timed. There is an internal delay between the user
setting the WR control bit and the automatic clearing of
the WR control bit when the programming operation is
complete. Please refer to
Characteristics and Timing Requirements”
detailed information about the delays associated with
various programming operations.
TABLE 5-2:
FIGURE 5-5:
© 2010 Microchip Technology Inc.
0x404F
0x404D
0x404C
0x4042
NVMCON
Value
V
PGDx
PGCx
MCLR
DD
5-3) and initiating the programming by setting
operation
Flash Memory Programming in
ICSP Mode
PROGRAMMING OPERATIONS
Erase all code memory, executive
memory and CodeGuard™ Configuration
registers (does not erase Unit ID or
Device ID registers).
Erase General Segment and FGS
Configuration register.
Erase Secure Segment and FSS
Configuration register. This operation will
also erase the General Segment and
FGS Configuration register.
Erase a page of code memory or
executive memory.
NVMCON ERASE OPERATIONS
P14
(Table
P6
ENTERING ICSP™ MODE
Erase Operation
5-2)
P21
Section 8.0 “AC/DC
or
P18
write
V
b31
IH
0
operation
b30
1
Program/Verify Entry Code = 0x4D434851
b29
for
0
b28
P1A
0
P1B
b27
TABLE 5-3:
5.4.2
The WR bit (NVMCON<15>) is used to start an erase
or write cycle. Setting the WR bit initiates the
programming cycle.
All erase and write cycles are self-timed. The WR bit
should be polled to determine if the erase or write cycle
has been completed. Starting a programming cycle is
performed as follows:
1
0x4001
0x4000
0x4003
NVMCON
Value
...
BSET
b3
0
STARTING AND STOPPING A
PROGRAMMING CYCLE
Program 1 row (64 instruction words)
of code memory or executive memory.
Write a Configuration register byte.
Program a code memory word.
NVMCON, #WR
NVMCON WRITE OPERATIONS
b2
0
b1
0
V
IH
Write Operation
b0
1
P19
DS70152H-page 35
P7