MC68HC11E1CFNE3R Freescale Semiconductor, MC68HC11E1CFNE3R Datasheet - Page 65
MC68HC11E1CFNE3R
Manufacturer Part Number
MC68HC11E1CFNE3R
Description
MCU 8-BIT 512 RAM 3MHZ 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC11r
Datasheet
1.MC68HC11E0CFNE2R.pdf
(242 pages)
Specifications of MC68HC11E1CFNE3R
Core Processor
HC11
Core Size
8-Bit
Speed
3MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
38
Program Memory Type
ROMless
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Processor Series
HC11E
Core
HC11
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SCI, SPI
Maximum Clock Frequency
3 MHz
Number Of Programmable I/os
38
Number Of Timers
8
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Program Memory Size
-
Lead Free Status / Rohs Status
Details
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Chapter 4
Central Processor Unit (CPU)
4.1 Introduction
Features of the M68HC11 Family include:
The CPU is designed to treat all peripheral, input/output (I/O), and memory locations identically as
addresses in the 64-Kbyte memory map. This is referred to as memory-mapped I/O. There are no special
instructions for I/O that are separate from those used for memory. This architecture also allows accessing
an operand from an external memory location with no execution time penalty.
4.2 CPU Registers
M68HC11 CPU registers are an integral part of the CPU and are not addressed as if they were memory
locations. The seven registers, discussed in the following paragraphs, are shown in
Freescale Semiconductor
•
•
•
•
•
Central processor unit (CPU) architecture
Data types
Addressing modes
Instruction set
Special operations such as subroutine calls and interrupts
15
7
A
Figure 4-1. Programming Model
M68HC11E Family Data Sheet, Rev. 5.1
0
SP
PC
D
IX
IY
7
7
S
X
H
I
B
N
Z
V
C
0
0
0
8-BIT ACCUMULATORS A & B
OR 16-BIT DOUBLE ACCUMULATOR D
INDEX REGISTER X
INDEX REGISTER Y
STACK POINTER
PROGRAM COUNTER
CONDITION CODES
CARRY/BORROW FROM MSB
OVERFLOW
ZERO
NEGATIVE
I-INTERRUPT MASK
HALF CARRY (FROM BIT 3)
X-INTERRUPT MASK
STOP DISABLE
Figure
4-1.
65
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