S912XEP100J5MAG Freescale Semiconductor, S912XEP100J5MAG Datasheet - Page 1064

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S912XEP100J5MAG

Manufacturer Part Number
S912XEP100J5MAG
Description
MCU 64K FLASH 144-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of S912XEP100J5MAG

Core Processor
HCS12X
Core Size
16-Bit
Speed
50MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
119
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 24x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Chapter 27 512 KByte Flash Module (S12XFTM512K3V1)
27.4.2.14 Set Field Margin Level Command
The Set Field Margin Level command, valid in special modes only, causes the Memory Controller to set
the margin level specified for future read operations of a specific P-Flash or D-Flash block.
Upon clearing CCIF to launch the Set Field Margin Level command, the Memory Controller will set the
field margin level for the targeted block and then set the CCIF flag.
1064
FERSTAT
Register
FSTAT
User margin levels can be used to check that Flash memory contents have
adequate margin for normal level read operations. If unexpected results are
encountered when checking Flash memory contents at user margin levels, a
potential loss of information has been detected.
CCOBIX[2:0]
Table 27-60. Set Field Margin Level Command FCCOB Requirements
000
001
MGSTAT1
MGSTAT0
EPVIOLIF
ACCERR
Table 27-59. Set User Margin Level Command Error Handling
Error Bit
FPVIOL
1. Read margin to the erased state
2. Read margin to the programmed state
(CCOBIX=001)
Table 27-58. Valid Set User Margin Level Settings
0x0002
CCOB
MC9S12XE-Family Reference Manual , Rev. 1.23
Set if CCOBIX[2:0] != 001 at command launch
Set if a Load Data Field command sequence is currently active
Set if command not available in current mode (see
Set if an invalid global address [22:16] is supplied
Set if an invalid margin level setting is supplied
None
None
None
None
0x0E
NOTE
User Margin-0 Level
FCCOB Parameters
Margin level setting
Level Description
Global address [22:16] to identify the Flash
Error Condition
(2)
block
Table
27-30)
Freescale Semiconductor

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