S912XEP100J5MAG Freescale Semiconductor, S912XEP100J5MAG Datasheet - Page 553

• Manufacturer Part Number: S912XEP100J5MAG
• Description: MCU 64K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S912XEP100J5MAG

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 119
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 24x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.3.2.16 Pulse Accumulator A Flag Register (PAFLG)
Read: Anytime
Write used in the flag clearing mechanism. Writing a one to the flag clears the flag. Writing a zero will not
affect the current status of the bit.
All bits reset to zero.
PAFLG indicates when interrupt conditions have occurred. The flags can be cleared via the normal flag
clearing mechanism (writing a one to the flag) or via the fast flag clearing mechanism (Reference TFFCA
bit in
14.3.2.17 Pulse Accumulators Count Registers (PACN3 and PACN2)
Freescale Semiconductor
Module Base + 0x0021
Module Base + 0x0022
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
PAOVF
Reset
Reset
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Field
PAIF
1
0
Section 14.3.2.6, “Timer System Control Register 1
W
W
R
R
PACNT7(15) PACNT6(14) PACNT5(13) PACNT4(12) PACNT3(11) PACNT2(10)
Pulse Accumulator A Overflow Flag — Set when the 16-bit pulse accumulator A overflows from 0xFFFF to
0x0000, or when 8-bit pulse accumulator 3 (PAC3) overflows from 0x00FF to 0x0000.
When PACMX = 1, PAOVF bit can also be set if 8-bit pulse accumulator 3 (PAC3) reaches 0x00FF followed by
an active edge on IC3.
Pulse Accumulator Input edge Flag — Set when the selected edge is detected at the IC7 input pin. In event
mode the event edge triggers PAIF and in gated time accumulation mode the trailing edge of the gate signal at
the IC7 input pin triggers PAIF.
0
0
0
7
7
When TFFCA = 1, the flags cannot be cleared via the normal flag clearing
mechanism (writing a one to the flag). Reference
System Control Register 1
= Unimplemented or Reserved
Figure 14-38. Pulse Accumulators Count Register 3 (PACN3)
Figure 14-37. Pulse Accumulator A Flag Register (PAFLG)
0
0
0
6
6
MC9S12XE-Family Reference Manual Rev. 1.23
Table 14-22. PAFLG Field Descriptions
5
0
0
5
0
(TSCR1)”.
NOTE
0
0
0
4
4
Description
(TSCR1)”).
0
0
0
3
3
Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
Section 14.3.2.6, “Timer
2
0
0
2
0
PACNT1(9)
PAOVF
0
0
1
1
PACNT0(8)
PAIF
0
0
0
0
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