S912XEP100J5MAG Freescale Semiconductor, S912XEP100J5MAG Datasheet - Page 765

• Manufacturer Part Number: S912XEP100J5MAG
• Description: MCU 64K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S912XEP100J5MAG

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 119
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 24x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

21.2
This section lists the name and description of all ports including inputs and outputs that do, or may, connect
off chip. The SPI module has a total of four external pins.
21.2.1
This pin is used to transmit data out of the SPI module when it is configured as a master and receive data
when it is configured as slave.
21.2.2
This pin is used to transmit data out of the SPI module when it is configured as a slave and receive data
when it is configured as master.
Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
Bus Clock
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Interrupt
Request
SPI
External Signal Description
MOSI — Master Out/Slave In Pin
MISO — Master In/Slave Out Pin
SPPR
SPI
SPI Baud Rate Register
Prescaler
SPI Control Register 1
SPI Control Register 2
Baud Rate Generator
SPI Status Register
SPI Data Register
Interrupt Control
SPIF
3
SPR
MODF
Clock Select
Counter
MC9S12XE-Family Reference Manual Rev. 1.23
SPTEF
3
Figure 21-1. SPI Block Diagram
Baud Rate
LSBFE=1
LSBFE=0
Control
Control
Master
Slave
Master Baud Rate
Slave Baud Rate
MSB
2
2
Shifter
LSBFE=1
LSBFE=0
LSBFE=0
LSBFE=1
CPOL
Clock
Shift
Phase +
Polarity
Control
Phase +
Polarity
Control
Chapter 21 Serial Peripheral Interface (S12SPIV5)
LSB
CPHA
BIDIROE
SPC0
Sample
Clock
Data Out
SCK In
SCK Out
Data In
Control
Logic
Port
MOSI
SCK
SS
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